US4390892A
Expired / Lapsed
US
⏱️ 0.0 years remaining
TV Sync generator system for PAL standards
Assignee: RCA Corp
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Filing: 1981-10-20
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Granted: 1983-06-28
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Expires: 2001-10-20
Abstract
Abstract A sync generator system for PAL-B television features an offset subcarrier generator that provides an offset subcarrier signal that has phase steps of ninety degree magnitude and occur twice per field. This makes smoothing of a PLL error voltage relatively easy.
Inventors
- 👤 Arthur J. Banks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:34
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/44; H04N9/45
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
113 words
A PAL television synchronization generator system comprising a quadrature subcarrier generator having an input for receiving a reference frequency signal and an output means for providing a pair of quadrature phase related subcarrier signals; an offset subcarrier generator having an input coupled to said quadrature generator output means and an output means for providing a subcarrier signal that is frequency offset with respect to said quadrature subcarrier signals and having phase steps of ninety degrees of the subcarrier signal occurring twice per field; and a phase locked loop having an error signal and coupled to said offset subcarrier generator output means; whereby said error signal in said phase locked loop is easily filtered.
Claim 2
Dependent Claim
113 words
A PAL television synchronization generator system comprising a quadrature subcarrier generator having an input for receiving a reference frequency signal and an output means for providing a pair of quadrature phase related subcarrier signals; an offset subcarrier generator having an input coupled to said quadrature generator output means and an output means for providing a subcarrier signal that is frequency offset with respect to said quadrature subcarrier signals and having phase steps of ninety degrees of the subcarrier signal occurring twice per field; and a phase locked loop having an error signal and coupled to said offset subcarrier generator output means; whereby said error signal in said phase locked loop is easily filtered.
Claim 3
Dependent Claim
65 words
A system as claimed in claim 1, further comprising a source of quadrature frame rate signals, and wherein said offset subcarrier generator comprises a pair of exclusive OR gates each having first and second inputs and an output, said first inputs respectively receiving said quadrature subcarrier signals, said second inputs respectively receiving said quadrature frame rate signals, and a trigger circuit coupled to said outputs.
Claim 4
Dependent Claim
72 words
A system as claimed in claim 2, wherein said trigger circuit comprises a NAND gate and an inverting input AND gate, each of said gates having a first input coupled to one of said exclusive OR gate outputs, a second input coupled to the remaining exclusive OR gate output, and an output; an inverter coupled to said AND gate output; and a flip-flop coupled to said inverter and said NAND gate output.
Claim 5
Dependent Claim
19 words
A system as claimed in claim 1, wherein said reference signal has a frequency of twice the subcarrier frequency.
Claim 6
Dependent Claim
107 words
A system as claimed in claim 1, wherein said quadrature subcarrier generator further comprises another output means for providing a third subcarrier signal in phase quadrature with respect to one of said pair of quadrature phase related subcarrier signals, and further comprising a PAL switcher having a pair of inputs for respectively receiving one of said pair of quadrature phase related subcarrier signals and said third subcarrier signal and an output means for providing the signals at said inputs in line alternate fashion, the remaining one of subcarrier signals and the output signal from said PAL switcher being adapted to be respectively coupled to a chroma encoder.
Claim 7
Dependent Claim
46 words
A system as claimed in claim 1, wherein said phase locked loop comprises a phase and frequency detector, a low pass filter coupled to said detector, a clock oscillator coupled to said filter, and a synchronization generator circuit coupled to said clock oscillator and said detector.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-06-27 | 1986-12-27 | 1987-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-06-27 | 1990-12-27 | 1991-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-06-27 | 1994-12-27 | 1995-06-28 | $7700.00 | Window Closed / Lapsed |