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US4394181A Expired / Lapsed US ⏱️ 0.0 years remaining

Methods of manufacturing a semiconductor device having a channel region spaced inside channel stoppers

Assignee: US Philips Corp
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Filing: 1981-09-28
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Granted: 1983-07-19
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Expires: 2001-09-28
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Abstract

Abstract A method of manufacturing an insulated gate field effect transistor includes the provision of a first masking layer on a semiconductor body followed by the introduction of a dopant characteristic of the conductivity type of the semiconductor body into unmasked areas to form a channel stopper. The unmasked areas are then oxidized to form an inset oxide layer. Subsequently, the masking layer is removed to expose a window in the oxide layer, and then a second masking layer is provided on the oxide layer. The second masking layer includes a second window extending into the first window so that the sides of the second window are situated within the first window. The sides of the second window determine the width of the channel region in a subsequent implantation of ions characteristic of the conductivity type of the channel region. Consequently, the channel region is spaced apart from the channel stoppers, and a very narrow channel region, for example 2 micrometers, is provided.

Inventors

  • 👤 Keith H. Nicholas

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 12:50
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10P; H10P30/00; H10P30/20; H10P30/22; H10P76/00; H10P76/40

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 199 words
A method of manufacturing a semiconductor device with an insulated gate field effect transistor having a channel region comprising the steps of providing a first masking layer on a major surface of a semiconductor body of one conductivity type, introducing a dopant into unmasked areas of said semiconductor body through said first masking layer to form channel stoppers of said one conductivity type, said channel stoppers having a higher concentration of said dopant than adjoining portions of said semiconductor body, oxidizing said unmasked areas of said semiconductor body to form an oxide layer inset on said semiconductor body, said channel stoppers being present below said inset oxide layer, removing said first masking layer to expose a first window bounded by said inset oxide layer, providing a second masking layer on said inset oxide layer and inside said first window for masking against ion implantation, said second masking layer providing a second window having sides parallel to the channel length situated within said first window, said sides determining the width of the channel region to be spaced apart from said channel stoppers, and implanting ions characteristic of a second conductivity type through said second window to form said channel region.
Claim 2
Independent Claim 199 words
A method of manufacturing a semiconductor device with an insulated gate field effect transistor having a channel region comprising the steps of providing a first masking layer on a major surface of a semiconductor body of one conductivity type, introducing a dopant into unmasked areas of said semiconductor body through said first masking layer to form channel stoppers of said one conductivity type, said channel stoppers having a higher concentration of said dopant than adjoining portions of said semiconductor body, oxidizing said unmasked areas of said semiconductor body to form an oxide layer inset on said semiconductor body, said channel stoppers being present below said inset oxide layer, removing said first masking layer to expose a first window bounded by said inset oxide layer, providing a second masking layer on said inset oxide layer and inside said first window for masking against ion implantation, said second masking layer providing a second window having sides parallel to the channel length situated within said first window, said sides determining the width of the channel region to be spaced apart from said channel stoppers, and implanting ions characteristic of a second conductivity type through said second window to form said channel region.
Claim 3
Dependent Claim 27 words
A method according to claim 1, wherein said second masking layer is an electron sensitive resist, and wherein said second window is defined by electron beam lithography.
Claim 4
Dependent Claim 32 words
A method according to claim 1, wherein said ions implanted through said first and second windows are n-conductivity type, and wherein the insulated gate field effect transistor is an n-channel depletion MOST.
Claim 5
Dependent Claim 28 words
A method according to claim 1, wherein said first window has said width greater than 4 micrometers and said second window has said width less than 4 micrometers.
Claim 6
Dependent Claim 28 words
A method according to claim 1, wherein said first window has said width of approximately 5 micrometers and said second window has said width of approximately 2 micrometers.
Claim 7
Dependent Claim 17 words
A method according to claim 1, wherein said second window is situated entirely within said first window.
Claim 8
Dependent Claim 26 words
A method according to claim 1, wherein said channel region has a concentration of implanted ions less than said concentration of dopant in said channel stoppers.
Claim 9
Dependent Claim 28 words
A method according to claim 2, wherein said first window has said width greater than 4 micrometers and said second window has said width less than 4 micrometers.
Claim 10
Dependent Claim 28 words
A method according to claim 8, wherein said first window has said width of approximately 5 micrometers and said second window has said width of approximately 2 micrometers.
Claim 11
Dependent Claim 17 words
A method according to claim 9, wherein said second window is situated entirely within said first window.

References Cited (Backward Citations)

US4135955A Cited
US4216573A Cited
US4277882A Cited
US4235011A Cited
US4294002A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-07-18 1987-01-17 1987-07-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-07-18 1991-01-17 1991-07-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-07-18 1995-01-17 1995-07-19 $7700.00 Window Closed / Lapsed

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