US4398105A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Arbiter circuit
Assignee: Signetics Corp
•
Filing: 1981-01-22
•
Granted: 1983-08-09
•
Expires: 2001-01-22
Abstract
Abstract An arbiter circuit includes a latch made of two crosscoupled NAND gates, one of which is a Schmitt NAND gate, a difference detector, and two output NOR gates. The output of the latch is coupled to the difference detector and to one input of the NOR gates. The NOR gates receive another input from the difference detector. The difference detector is responsive to a voltage difference that exceeds one V BE , thereby blocking signals that originate in the latch during oscillating or metastable states of the latch, which may include rut pulses.
Inventors
- 👤 Philip J. Keller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:25
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0375; H03K5/00; H03K5/22; H03K5/26
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
132 words
An arbiter circuit, comprising: (a) first and second input terminals and first and second output terminals; (b) first and second cross-coupled NAND gates coupled to said first and second input terminals, respectively; (c) a difference detector gate coupled to the outputs of said cross-coupled NAND gates and responsive to a voltage difference exceeding a specified amount; (d) first and second NOR gates having their outputs coupled to said first and second output terminals, respectively; (e) means coupling a first input of each of said NOR gates to the output of said difference detector gate, and (f) means coupling the output of said first NAND gate to a second input of said first NOR gate and coupling the output of said second NAND gate to a second input of said second NOR gate.
Claim 2
Dependent Claim
132 words
An arbiter circuit, comprising: (a) first and second input terminals and first and second output terminals; (b) first and second cross-coupled NAND gates coupled to said first and second input terminals, respectively; (c) a difference detector gate coupled to the outputs of said cross-coupled NAND gates and responsive to a voltage difference exceeding a specified amount; (d) first and second NOR gates having their outputs coupled to said first and second output terminals, respectively; (e) means coupling a first input of each of said NOR gates to the output of said difference detector gate, and (f) means coupling the output of said first NAND gate to a second input of said first NOR gate and coupling the output of said second NAND gate to a second input of said second NOR gate.
Claim 3
Dependent Claim
18 words
The invention according to claim 1, wherein one of said NAND gates comprises a Schmitt trigger NAND gate.
Claim 4
Dependent Claim
64 words
The invention according to claim 1, and further including: (g) a first inverter coupled to feed back a signal from the output of said first NOR gate to a third input of said second NAND gate, and (h) a second inverter coupled to feed back a signal from the output of said second NOR gate to a third input of said first NAND gate.
Claim 5
Dependent Claim
23 words
The invention according to claim 1, wherein said difference detector gate is responsive to a voltage difference of about 1 V BE .
References Cited (Backward Citations)
US3646455A
Cited
US3764902A
Cited
US3761739A
Cited
US3983496A
Cited
US4093878A
Cited
US4339731A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-08 | 1987-02-07 | 1987-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-08 | 1991-02-07 | 1991-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-08 | 1995-02-07 | 1995-08-09 | $7700.00 | Window Closed / Lapsed |