Integrated circuit with at least three ground pads

Claim 2

In a semiconductor integrated circuit device for audio amplifier circuits including a semiconductor substrate, first and second semiconductor island regions formed on said semiconductor substrate, an input amplifier circuit formed in said first semiconductor island region, an output amplifier circuit formed in said second semiconductor island region, a first wire bonding pad which is formed on said semiconductor substrate for grounding said input amplifier circuit and a first externally connecting terminal which is provided being separated away from said semiconductor substrate and which is electrically connected to said first wire bonding pad via a first metal wire to ground said input amplifier circuit, the improvement comprising a second wire bonding pad which is formed on said semiconductor substrate being separated away from said first wire bonding pad for grounding said output amplifier circuit, a second externally connecting terminal which is provided being separated away from said semiconductor substrate and which is electrically connected to said second wire bonding pad via a second metal wire to ground said output amplifier circuit, a third wire bonding pad which is formed in the vicinity of the second semiconductor island region on said semiconductor substrate being separated away from said first and second wire bonding pads for grounding said semiconductor substrate, and a third metal wire which electrically connects said third wire bonding pad to said second externally connecting terminal to ground said semiconductor substrate.

Claim 3

A semiconductor integrated circuit device for audio amplifier circuits according to claim 1, wherein said device further comprises an element forming region for forming a PNP transistor that constitutes said input amplifier circuit, said element forming region being formed in said first semiconductor island region, and a connection wiring which electrically connects the semiconductor substrate in the vicinity of said element forming region to said third wire bonding pad.

Claim 4

A semiconductor integrated circuit device for audio amplifier circuits according to claim 2, wherein said connection wiring is electrically connected to said semiconductor substrate in the vicinity of said element forming region, and is composed of a metal layer which stretches on said semiconductor substrate between the element forming region and said third wire bonding pad.

Claim 5

A semiconductor integrated circuit device which comprises a semiconductor substrate, first and second semiconductor island regions formed on said semiconductor substrate, a first circuit element formed in said first semiconductor island region, a second circuit element formed in said second semiconductor island region, a first wire bonding pad formed on said semiconductor substrate and electrically connected to said first circuit element to provide a predetermined reference potential to said first circuit element, a second wire bonding pad formed on said semiconductor substrate and being electrically connected to said second circuit element to provide said reference potential to said second circuit element, a third wire bonding pad formed on said semiconductor substrate to provide said reference potential to said semiconductor substrate, and a conductive layer formed on said semiconductor substrate and electrically connected to said third wire bonding pad and said semiconductor substrate.

Claim 6

A semiconductor integrated circuit device which comprises a semiconductor substrate, first and second semiconductor island regions formed on said semiconductor substrate, a first circuit element formed in said first semiconductor island region, a second circuit element formed in said second semiconductor island region, a first wire bonding pad formed on said semiconductor substrate and electrically connected to said first circuit element to provide a predetermined reference potential to said first circuit element, a second wire bonding pad formed on said semiconductor substrate and being electrically connected to said second circuit element to provide said reference potential to said second circuit element, a third wire bonding pad formed on said semiconductor substrate to provide said reference potential to said semiconductor substrate, and a conductive layer formed on said semiconductor substrate and electrically connected to said third wire bonding pad and said semiconductor substrate.

Claim 7

A semiconductor integrated circuit device according to claim 4, wherein said first circuit element constitutes a PNP transistor.

Claim 8

A semiconductor integrated circuit device according to claim 4, wherein said conductive layer is made of aluminum.

Claim 9

A semiconductor integrated circuit device which comprises a semiconductor substrate, first and second semiconductor island regions formed on said semiconductor substrate and separated away from each other by a semiconductor isolation region contacted with said semiconductor substrate, a first circuit element formed in said first semiconductor island region, a second circuit element formed in said second semiconductor island region, a first bonding pad formed on said semiconductor substrate and electrically connected to said first circuit element to provide a predetermined reference potential to said first circuit element, a second bonding pad formed on said semiconductor substrate and electrically connected to said second circuit element to provide said reference potential to said second circuit element, a third bonding pad formed on said semiconductor substrate to provide said reference potential to said semiconductor substrate, and a conductive layer formed on said semiconductor substrate and contacted with said third bonding pad, with a first portion of said semiconductor isolation region in the vicinity of said first circuit element and with a second portion of said semiconductor isolation region in the vicinity of said second circuit element.

Claim 10

A semiconductor integrated circuit device which comprises a semiconductor substrate, first and second semiconductor island regions formed on said semiconductor substrate and separated away from each other by a semiconductor isolation region contacted with said semiconductor substrate, a first circuit element formed in said first semiconductor island region, a second circuit element formed in said second semiconductor island region, a first bonding pad formed on said semiconductor substrate and electrically connected to said first circuit element to provide a predetermined reference potential to said first circuit element, a second bonding pad formed on said semiconductor substrate and electrically connected to said second circuit element to provide said reference potential to said second circuit element, a third bonding pad formed on said semiconductor substrate to provide said reference potential to said semiconductor substrate, and a conductive layer formed on said semiconductor substrate and contacted with said third bonding pad, with a first portion of said semiconductor isolation region in the vicinity of said first circuit element and with a second portion of said semiconductor isolation region in the vicinity of said second circuit element.

Claim 11

A semiconductor integrated circuit device according to claim 7, wherein said conductive layer is made of aluminum.

Claim 12

A semiconductor integrated circuit device which comprises a semiconductor substrate, first and second semiconductor island regions formed on said semiconductor substrate and separated away from each other by a semiconductor isolation region contacted with said semiconductor substrate, a first amplifier circuit formed in said first semiconductor island region, a second amplifier circuit formed in said second semiconductor island region, a first connecting pad which is formed on said semiconductor substrate for grounding said first amplifier circuit, a first externally connecting terminal which is provided being separated away from said semiconductor substrate and which is electrically connected to said first connecting pad to ground the first amplifier circuit, a second connecting pad which is formed on said semiconductor substrate being separated away from said first connecting pad for grounding said second amplifier circuit, a second externally connecting terminal which is provided being separated away from said semiconductor substrate and which is electrically connected to said second connecting pad to ground said second amplifier circuit, a third connecting pad which is formed on said semiconductor substrate being separated away from said first and second connecting pads, and a conductive layer formed on said semiconductor substrate and contacted with said third connecting pad, and which is also contacted with a first portion of said semiconductor isolation region in the vicinity of said first semiconductor island region and with a second portion of said semiconductor isolation region in the vicinity of said second semiconductor island region, and wherein said third connecting pad is electrically contacted to said second externally connecting terminal to ground said semiconductor substrate.

Claim 13

A semiconductor integrated circuit device which comprises a semiconductor substrate, first and second semiconductor island regions formed on said semiconductor substrate and separated away from each other by a semiconductor isolation region contacted with said semiconductor substrate, a first amplifier circuit formed in said first semiconductor island region, a second amplifier circuit formed in said second semiconductor island region, a first connecting pad which is formed on said semiconductor substrate for grounding said first amplifier circuit, a first externally connecting terminal which is provided being separated away from said semiconductor substrate and which is electrically connected to said first connecting pad to ground the first amplifier circuit, a second connecting pad which is formed on said semiconductor substrate being separated away from said first connecting pad for grounding said second amplifier circuit, a second externally connecting terminal which is provided being separated away from said semiconductor substrate and which is electrically connected to said second connecting pad to ground said second amplifier circuit, a third connecting pad which is formed on said semiconductor substrate being separated away from said first and second connecting pads, and a conductive layer formed on said semiconductor substrate and contacted with said third connecting pad, and which is also contacted with a first portion of said semiconductor isolation region in the vicinity of said first semiconductor island region and with a second portion of said semiconductor isolation region in the vicinity of said second semiconductor island region, and wherein said third connecting pad is electrically contacted to said second externally connecting terminal to ground said semiconductor substrate.

Claim 14

A semiconductor integrated circuit device according to claim 9, wherein said first and second amplifier circuits constitute input and output amplifier circuits, respectively.

Claim 15

A semiconductor integrated circuit device according to claim 9, wherein said first and second amplifier circuits constitute output and input amplifier circuits, respectively.

Claim 16

A semiconductor integrated circuit device according to claim 9, 10 or 11, wherein said conductive layer is made of aluminum.

Claim 17

A semiconductor integrated circuit device which comprises a semiconductor substrate which is of a first conductivity type and has one main surface, a semiconductor layer which is of a second conductivity type opposite to said first conductivity type and is provided on said main surface, a semiconductor isolation region of said first conductivity type which is formed in said semiconductor layer and which reaches to said main surface to form first and second island portions of said semiconductor layer, a plurality of semiconductor regions for a first amplifier circuit which are of said first conductivity type and are formed in said first island portion, a plurality of semiconductor regions for a second amplifier circuit which are of said first conductivity type and are formed in said second island portion, an insulating layer which is provided on said semiconductor isolation region and which includes first and second insulating layer portions formed on said first and second semiconductor island regions, respectively, a first connecting pad which is formed on the first insulating layer portion of said insulating layer and which is electrically connected to at least one of said semiconductor regions for said first amplifier circuit to provide a predetermined reference potential to said first amplifier circuit, a second connecting pad which is formed on the second insulating layer portion of said insulating layer spaced from said first portion and which is electrically connected to at least one of said semiconductor regions for said second amplifier circuit to provide said predetermined reference potential to said second amplifier circuit, a third connecting pad which is formed on a part of said semiconductor isolation region adjacent to said one of said semiconductor regions for said first amplifier circuit and which is electrically contacted to said part of said semiconductor isolation region to provide said predetermined reference potential to said semiconductor isolation region, and a conductive layer formed on said insulating layer and which is electrically contacted to said third connecting pad and another part of said semiconductor isolation region adjacent to said one of said semiconductor regions for said second amplifier circuit and which is electrically contacted to said other part of said semiconductor isolation region.

Claim 18

A semiconductor integrated circuit device which comprises a semiconductor substrate which is of a first conductivity type and has one main surface, a semiconductor layer which is of a second conductivity type opposite to said first conductivity type and is provided on said main surface, a semiconductor isolation region of said first conductivity type which is formed in said semiconductor layer and which reaches to said main surface to form first and second island portions of said semiconductor layer, a plurality of semiconductor regions for a first amplifier circuit which are of said first conductivity type and are formed in said first island portion, a plurality of semiconductor regions for a second amplifier circuit which are of said first conductivity type and are formed in said second island portion, an insulating layer which is provided on said semiconductor isolation region and which includes first and second insulating layer portions formed on said first and second semiconductor island regions, respectively, a first connecting pad which is formed on the first insulating layer portion of said insulating layer and which is electrically connected to at least one of said semiconductor regions for said first amplifier circuit to provide a predetermined reference potential to said first amplifier circuit, a second connecting pad which is formed on the second insulating layer portion of said insulating layer spaced from said first portion and which is electrically connected to at least one of said semiconductor regions for said second amplifier circuit to provide said predetermined reference potential to said second amplifier circuit, a third connecting pad which is formed on a part of said semiconductor isolation region adjacent to said one of said semiconductor regions for said first amplifier circuit and which is electrically contacted to said part of said semiconductor isolation region to provide said predetermined reference potential to said semiconductor isolation region, and a conductive layer formed on said insulating layer and which is electrically contacted to said third connecting pad and another part of said semiconductor isolation region adjacent to said one of said semiconductor regions for said second amplifier circuit and which is electrically contacted to said other part of said semiconductor isolation region.

Claim 19

A semiconductor integrated circuit according to claim 13, wherein said reference potential is a ground potential.

Claim 20

A semiconductor integrated circuit device according to claim 13, wherein said conductive layer comprises aluminum.