US4403307A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1980-11-06
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Granted: 1983-09-06
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Expires: 2000-11-06
Abstract
Abstract The present invention discloses a semiconductor memory device composed of double gate type field effect transistors which have control gate and floating gate for accumulating charges. The conditions for optimum charge injection writing and for optimum reading of this semiconductor memory device are mutually inconsistent. In order to satisfy said two conditions, the present invention provides a charge injection transistor and a read transistor, wherein the floating gate of both transistors are electrically connected, the control gates are connected to a first signal lines, the drains are connected respectively to the different second and third signal lines and the sources are grounded.
Inventors
- 👤 Koh-ichi Maeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:36
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356008; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
161 words
A semiconductor memory device, comprising: a substrate having a first conductivity type; a charge injection (write) transistor and a read transistor fabricated on the substrate, each transistor including source and drain regions which are formed in isolation on the substrate and which have a second conductivity type, a conductive floating gate between said source region and drain region and spaced apart from the substrate, a control gate spaced apart from said floating gate, and insulator means for mutually insulating the substrate, floating gate, and control gate; means for electrically connecting said floating gates of said charge injection transistor and said read transistor; means for connecting said control gates of said charge injection transistor and said read transistor in common to a first signal line; means for respectively connecting said drains of said charge injection transistor and said read transistor to different second and third signal lines; and means for connecting the sources of the charge injection transistor and the read transistor.
Claim 2
Dependent Claim
161 words
A semiconductor memory device, comprising: a substrate having a first conductivity type; a charge injection (write) transistor and a read transistor fabricated on the substrate, each transistor including source and drain regions which are formed in isolation on the substrate and which have a second conductivity type, a conductive floating gate between said source region and drain region and spaced apart from the substrate, a control gate spaced apart from said floating gate, and insulator means for mutually insulating the substrate, floating gate, and control gate; means for electrically connecting said floating gates of said charge injection transistor and said read transistor; means for connecting said control gates of said charge injection transistor and said read transistor in common to a first signal line; means for respectively connecting said drains of said charge injection transistor and said read transistor to different second and third signal lines; and means for connecting the sources of the charge injection transistor and the read transistor.
Claim 3
Dependent Claim
29 words
A semiconductor memory device as claimed in claim 1, wherein the electrical characteristics of said charge injection (write) transistor are different from the electrical characteristics of said read transistor.
Claim 4
Dependent Claim
37 words
A semiconductor memory device as claimed in claim 2, wherein the impurity concentration of said substrate portion between said source region and drain region of said charge injection transistor is higher than that of said read transistor.
Claim 5
Dependent Claim
75 words
A semiconductor memory device as claimed in claim 1, wherein charge is applied to the floating gate of said charge injection transistor by applying a predetermined voltage to said first signal line and a predetermined write voltage to the second signal line, and the stored information is read by applying a predetermined read voltage to said first signal line and detecting the degree of conductance of said read transistor via the said third signal line.
Claim 6
Dependent Claim
46 words
A semiconductor memory device as claimed in claim 1, wherein said sources of said charge injection transistor and said read transistor comprise a common impurity diffused region, said floating gates comprise a common first conductive layer and said control gates comprise a common second conductive layer.
Claim 7
Dependent Claim
25 words
A semiconductor memory device as claimed in claim 5, wherein said first conductive layer and the second conductive layer are comprised of polycrystalline silicon layers.
Claim 8
Dependent Claim
101 words
A semiconductor memory device as claimed in claim 1, 2, 3, 4, 5 or 6, wherein there are a plurality of memory cells fabricated on the substrate, each memory cell including one said charge injection transistor and one said read transistor, said memory cells being arranged in the form of matrix, with said first signal lines being arranged in the row direction to serve as word lines, said second signal lines being arranged in the column direction to serve as charge injection bit lines, and said third signal lines being arranged in the column direction to serve as read-out bit lines.
Claim 9
Dependent Claim
44 words
A semiconductor memory device as claimed in claim 7, wherein said word lines comprise polycrystalline silicon layers, portions of said word lines serving as said control gates, and wherein said charge injection bit lines and said read-out bit lines are comprised of metal conductor.
Claim 10
Dependent Claim
92 words
A semiconductor memory device as claimed in claim 7, further comprising charge injection circuit means for generating a write voltage; sense circuit means for detecting the degree of conductance of said read transistors; column decoder circuit means for connecting, during the charge injection, the selected said charge injection bit lines and said charge injection circuit means and also for connecting, at the time of a read-out operation, selected said read-out bit lines and the sense circuit means; and word decoder circuit means for applying a predetermined voltage to the selected word lines.
Claim 11
Dependent Claim
78 words
A semiconductor memory device as claimed in claim 1, 2, 3, 4, 5, or 6, further comprising means for continuously connecting a voltage source to the drain of the read transistor; and a switching element having an input connected to the the drain said read transistor, said switching element being turned ON and OFF by differences in potential levels at the drain of said read transistor due to differences in the degrees of conductance of said read transistor.
Claim 12
Dependent Claim
104 words
A semiconductor memory device as claimed in claim 10, further comprising an amplifier having an output and an inverting input; an input resistor connected to the inverting input; a feedback resistor connected between the output and the inverting input; and a compensating resistor series-connected to said switching element, the series of the switching element and the compensating resistor being connected in parallel with one of the input resistor and the feedback resistor, the resistance value of one of said input resistor and feedback resistor being compensated in accordance with the charge on said floating gate for controlling the ON-OFF condition of said switching element.
References Cited (Backward Citations)
US4257056A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-05 | 1987-03-07 | 1987-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-05 | 1991-03-07 | 1991-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-05 | 1995-03-07 | 1995-09-06 | $7700.00 | Window Closed / Lapsed |