Multiplexed MOS multiaccess memory system

Claim 1

Multiplexed, multiaccess memory system for use with a digital data computer system of a type having a memory formed of a plurality of memory modules each containing data bit storage cells, the computer system further including a digital data processer providing address instructions to memory address multiplexers, the outputs of which are applied to decoders functioning responsively to said instructions to activate particular storage cells of a particular module and permit the logic state of said particular cell to be altered to reflect an instruction, the memory system comprising: a system address multiplexer having a plurality of inputs for receiving multiple addresses simultaneously from one or more processing units and having one or more addressing outputs a component address demultiplexer having an input coupled to said system address multiplexer and having a plurality of outputs, a multiaccess memory having a plurality of memory address registers, each being connected to one of said plurality of outputs of said component address demultiplexer and having a plurality of memory data registers, a system data multiplexer/demultiplexer having a plurality of terminals for receiving and transmitting data from and to said multiaccess memory according to corresponding specified addresses, and a component data multiplexer/demultiplexer coupled to said data registers and operating as a multiplexer when reading data from said memory data registers and operating as a demultiplexer when writing data into said memory data registers.