US4418094A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vertical-etch direct moat isolation process
Assignee: Texas Instruments Inc
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Filing: 1982-03-02
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Granted: 1983-11-29
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Expires: 2002-03-02
Abstract
Abstract Direct Moat Isolation for VLSI integrated circuit structures is formed by growing oxide over the entire substrate area, and then cutting windows in the oxide, using an anisotropic polymer-free oxide etch, where moat regions are to be formed. To prevent polysilicon filamentation, gate patterning is performed with an extremely selective polysilicon etch. The combination of these processing steps permits a direct moat isolation device fabrication process which is insensitive to the oxide sidewall angle, increasing yield and permitting extremely compact isolation structures to be formed.
Inventors
- 👤 Yee-Chaung See
- 👤 Roderick D. Davies
- 👤 Dennis C. Hartman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:07
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/268; H10P50/28; H10P50/282; H10P50/283; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
153 words
A process for forming integrated circuit device structures, comprising the steps of: providing a silicon substrate; forming a uniform oxide layer on said substrate; etching windows in said oxide to expose selected moat regions of said substrate; forming a thin gate oxide layer within said respective moat regions; depositing polysilicon on exposed surfaces; patterning said polysilicon to define selected gate regions within said moat regions; etching said polysilicon where exposed by said gate patterning step; forming a plurality of respective sources and drains within respective ones of said moats; and forming a plurality of respective contacts to respective ones of said sources, drains, and gates, wherein said oxide etch is anisotropic and selective over silicon, and does not deposit substantial quantities of polymers in said moat regions; and wherein said polysilicon etch is anisotropic and has a selectivity over oxide which is greater than 15; whereby an MOS integrated circuit structure is formed.
Claim 2
Dependent Claim
153 words
A process for forming integrated circuit device structures, comprising the steps of: providing a silicon substrate; forming a uniform oxide layer on said substrate; etching windows in said oxide to expose selected moat regions of said substrate; forming a thin gate oxide layer within said respective moat regions; depositing polysilicon on exposed surfaces; patterning said polysilicon to define selected gate regions within said moat regions; etching said polysilicon where exposed by said gate patterning step; forming a plurality of respective sources and drains within respective ones of said moats; and forming a plurality of respective contacts to respective ones of said sources, drains, and gates, wherein said oxide etch is anisotropic and selective over silicon, and does not deposit substantial quantities of polymers in said moat regions; and wherein said polysilicon etch is anisotropic and has a selectivity over oxide which is greater than 15; whereby an MOS integrated circuit structure is formed.
Claim 3
Dependent Claim
26 words
The process of claim 1, further comprising the step of: implanting said substrate with a field threshold/device threshold implant, prior to formation of said oxide layer.
Claim 4
Dependent Claim
25 words
The process of claim 2, wherein said substrate comprises a first conductivity type, and said implant comprises an additional concentration of said first conductivity type.
Claim 5
Dependent Claim
24 words
The process of claim 1, wherein said oxide etch comprises plasma etching in a mixture of CHF 3 and C 2 F 6 .
Claim 6
Dependent Claim
20 words
The process of claim 1, wherein said polysilicon patterning step comprises applying a patterned layer of a hard mask material.
Claim 7
Dependent Claim
13 words
The process of claim 5, wherein said hard mask material comprises silicon nitride.
Claim 8
Dependent Claim
24 words
The process of claims 1, 2, 3, 4, 5, or 6, wherein said polysilicon etch comprises applying RF power in an atmosphere comprising chlorine.
Claim 9
Dependent Claim
12 words
The process of claim 7, whrein said atmosphere consists essentially of chlorine.
Claim 10
Dependent Claim
11 words
The process of claim 8, wherein said atmosphere consists of chlorine.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-28 | 1987-05-30 | 1987-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-28 | 1991-05-30 | 1991-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-28 | 1995-05-30 | 1995-11-29 | $7700.00 | Window Closed / Lapsed |