US4419595A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog or gate circuit
Assignee: United States Department of the Air Force
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Filing: 1981-10-14
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Granted: 1983-12-06
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Expires: 2001-10-14
Abstract
Abstract The maximum instantaneous value of analog signals from multiple sources is detected by means of an analog OR gate circuit in which the analog signal from each input is connected to both a positive and a negative half wave rectifier circuit. The outputs of the positive half wave rectifier circuit are OR wired together and the outputs of the negative half wave rectifier circuits are OR wired together and the OR outputs of both are summed to provide an output signal that is the maximum peak instantaneous signal. Because the maximum instantaneous signal from any channel reverse biases the other rectifiers, other signals are neither added nor subtracted from the output.
Inventors
- 👤 Richard W. Reiner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:25
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/0038
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
107 words
An analog OR gate circuit for detecting the maximum instantaneous value of analog signals from multiple sources comprising: a multiplicity of gate circuit inputs, each receiving a discrete analog input signal, a gate circuit output, a positive half wave rectifier circuit connected to each said gate circuit input, a negative half wave rectifier circuit connected to each said gate circuit input, the outputs of said positive half wave rectifier circuits connected to provide an OR output, the outputs of said negative half wave rectifier circuits connected to provide an OR output, and summing means summing said OR outputs and providing an output to said gate circuit output.
Claim 2
Dependent Claim
107 words
An analog OR gate circuit for detecting the maximum instantaneous value of analog signals from multiple sources comprising: a multiplicity of gate circuit inputs, each receiving a discrete analog input signal, a gate circuit output, a positive half wave rectifier circuit connected to each said gate circuit input, a negative half wave rectifier circuit connected to each said gate circuit input, the outputs of said positive half wave rectifier circuits connected to provide an OR output, the outputs of said negative half wave rectifier circuits connected to provide an OR output, and summing means summing said OR outputs and providing an output to said gate circuit output.
Claim 3
Dependent Claim
287 words
An analog OR gate circuit as defined in claim 1 wherein each said positive half wave rectifier circuit comprises: an operational amplifier having a positive input and a negative input and an output, said positive input connected to ground, an input resistor connected between a gate circuit input and the negative input of said operational amplifier, a feedback resistor, and first and second half wave rectifiers, each having an anode and a cathode, the output of said operational amplifier connected to the cathode of said first rectifier and the anode of said second rectifier, the cathode of said second rectifier connected to the negative input of said operational amplifier, said feedback resistor connected between the negative input of said operational amplifier and the anode of said first rectifier, the junction of said feedback resistor and the anode of said first rectifier providing the half wave rectifier circuit output; and, wherein each said negative half wave rectifier circuit comprises: an operational amplifier having a positive input and a negative input and an output, said positive input connected to ground, an input resistor connected between a gate circuit input and the negative input of said operational amplifier, a feedback resistor, and first and second half wave rectifiers, each having an anode and a cathode, the output of said operational amplifier connected to the cathode of said first rectifier and the anode of said second rectifier, the anode of said first rectifier connected to the negative input of said operational amplifier, said feedback resistor connected between the negative input of said operational amplifier and the cathode of said second rectifier, the junction of said feedback resistor and the cathode of said second rectifier providing the half wave rectifier circuit output.
Claim 4
Dependent Claim
107 words
An analog OR gate circuit as defined in claim 2 wherein said summing means comprises an operational amplifier having an output, a negative input and a positive input, said positive input connected to ground and said output connected to said gate circuit output, an output resistor connected between the output and negative input of said operational amplifier, a first summing resistor connected between the the OR output of said positive half wave rectifier circuit and the negative input of said operational amplifier, and a second summing resistor connected between the OR output of said negative half wave rectifier circuit and the negative input of said operational amplifier.
Claim 5
Dependent Claim
35 words
An analog OR gate circuit as defined in claim 3 wherein the value of the resistance of said input resistor is equal to the resistance of said feedback resistor in each half wave rectifier circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-05 | 1987-06-06 | 1987-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-05 | 1991-06-06 | 1991-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-05 | 1995-06-06 | 1995-12-06 | $7700.00 | Window Closed / Lapsed |