US4419684A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Hitachi Ltd
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Filing: 1981-01-14
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Granted: 1983-12-06
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Expires: 2001-01-14
Abstract
Abstract Well regions of p-type are disposed in a surface region of an n-type Si substrate of a semiconductor integrated circuit. The p-type well regions are arranged in the shape of islands, and various semiconductor elements are formed in the p-type well islands. The substrate surface region between the p-type well islands is filled with a depletion layer, and an interconnection layer is disposed on an insulating film over that body region contained within the depletion layer.
Inventors
- 👤 Yoshio Sakai
- 👤 Hideo Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:15
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10W; H10W10/00; H10W10/01; H10W10/051; H10W10/50; H10W20/00; H10W20/40; H10W20/495
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
272 words
A semiconductor integrated circuit device comprising: a semiconductor body of a first conductivity type; an insulating layer disposed on a major surface of said semiconductor body; an interconnection layer disposed on said insulating layer so as to overlie a first portion of said semiconductor body, which first portion comprises a surface portion at said major surface and an interior portion formed in said semiconductor body under said surface portion, and wherein a series capacitance is formed of the capacitance across said insulating layer between said interconnection layer and said body and through a depletion layer formed in said body beneath said insulating layer, and further including means for reducing said series capacitance independently of the thickness of said insulating layer, wherein said reducing means includes means for increasing the depth of said depletion layer formed in said body, said means comprising a well-shaped semiconductor region of a second conductivity type, opposite said first conductivity type, formed to extend into said semiconductor body from said major surface thereof and forming a PN junction with said body, and means for biasing said PN junction so as to impart a depletion region from said well-shaped region into said interior portion of said first portion of said body beneath said interconnection layer, wherein said well-shaped region is disposed to at least partially surround said interior portion of said first portion on said major surface so that first and second regions of said well-shaped semiconductor region will face each other with said interior portion of said first portion being interposed between said first and second regions, and wherein said well-shaped semiconductor region contains semiconductor circuit elements therein.
Claim 2
Dependent Claim
272 words
A semiconductor integrated circuit device comprising: a semiconductor body of a first conductivity type; an insulating layer disposed on a major surface of said semiconductor body; an interconnection layer disposed on said insulating layer so as to overlie a first portion of said semiconductor body, which first portion comprises a surface portion at said major surface and an interior portion formed in said semiconductor body under said surface portion, and wherein a series capacitance is formed of the capacitance across said insulating layer between said interconnection layer and said body and through a depletion layer formed in said body beneath said insulating layer, and further including means for reducing said series capacitance independently of the thickness of said insulating layer, wherein said reducing means includes means for increasing the depth of said depletion layer formed in said body, said means comprising a well-shaped semiconductor region of a second conductivity type, opposite said first conductivity type, formed to extend into said semiconductor body from said major surface thereof and forming a PN junction with said body, and means for biasing said PN junction so as to impart a depletion region from said well-shaped region into said interior portion of said first portion of said body beneath said interconnection layer, wherein said well-shaped region is disposed to at least partially surround said interior portion of said first portion on said major surface so that first and second regions of said well-shaped semiconductor region will face each other with said interior portion of said first portion being interposed between said first and second regions, and wherein said well-shaped semiconductor region contains semiconductor circuit elements therein.
Claim 3
Dependent Claim
273 words
A semiconductor integrated circuit device comprising: a semiconductor body of a first conductivity type; an insulating layer diposed on a major surface of said semiconductor body; an interconnection layer disposed on said insulating layer so as to overlie a first portion of said semiconductor body, which first portion comprises a surface portion at said major surface and an interior portion formed in said semiconductor body under said surface portion, and wherein a series capacitance is formed of the capacitance across said insulating layer between said interconnection layer and said body and through a depletion layer formed in said body beneath said insulating layer, and further including means for reducing said series capacitance independently of the thickness of said insulating layer, wherein said reducing means includes means for increasing the depth of said depletion layer formed in said body, said means comprising at least first and second well-shaped semiconductor regions of a second conductivity type, opposite said first conductivity type, formed to extend into said semiconductor body from said major surface thereof and forming a PN junction with said body, and means for biasing said PN junction so as to impart depletion regions from said well-shaped regions into said interior portion of said first portion of said body beneath said interconnection layer, wherein said well-shaped regions are disposed to at least partially surround said interior portion of said first portion on said major surface so that said first and second well-shaped regions will face each other with said interior portion of said first portion being interposed between said first and second well-shaped regions, and wherein said well-shaped semiconductor regions contain semiconductor circuit elements therein.
Claim 4
Dependent Claim
273 words
A semiconductor integrated circuit device comprising: a semiconductor body of a first conductivity type; an insulating layer diposed on a major surface of said semiconductor body; an interconnection layer disposed on said insulating layer so as to overlie a first portion of said semiconductor body, which first portion comprises a surface portion at said major surface and an interior portion formed in said semiconductor body under said surface portion, and wherein a series capacitance is formed of the capacitance across said insulating layer between said interconnection layer and said body and through a depletion layer formed in said body beneath said insulating layer, and further including means for reducing said series capacitance independently of the thickness of said insulating layer, wherein said reducing means includes means for increasing the depth of said depletion layer formed in said body, said means comprising at least first and second well-shaped semiconductor regions of a second conductivity type, opposite said first conductivity type, formed to extend into said semiconductor body from said major surface thereof and forming a PN junction with said body, and means for biasing said PN junction so as to impart depletion regions from said well-shaped regions into said interior portion of said first portion of said body beneath said interconnection layer, wherein said well-shaped regions are disposed to at least partially surround said interior portion of said first portion on said major surface so that said first and second well-shaped regions will face each other with said interior portion of said first portion being interposed between said first and second well-shaped regions, and wherein said well-shaped semiconductor regions contain semiconductor circuit elements therein.
Claim 5
Dependent Claim
41 words
A semiconductor integrated circuit device according to claim 2, wherein the lateral extent of each of said depletion regions extending in a direction parallel to the surface of said body is such as to intersect a neighboring depletion region adjacent thereto.
Claim 6
Dependent Claim
33 words
A semiconductor integrated circuit device according to claim 3, wherein the shape of each of said depletion regions as viewed in a direction normal to the surface of said body is substantially square.
Claim 7
Dependent Claim
33 words
A semiconductor integrated circuit device according to claim 3, wherein the shape of each of said depletion regions as viewed in a direction normal to the surface of said body is substantially hexagonal.
Claim 8
Dependent Claim
40 words
A semiconductor integrated circuit device according to claim 2, wherein said interconnection layer extends longitudinally on the surface of said insulating layer and said first and second well-shaped regions extend longitudinally in parallel on opposite sides of said interconnection layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-05 | 1987-06-06 | 1987-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-05 | 1991-06-06 | 1991-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-05 | 1995-06-06 | 1995-12-06 | $7700.00 | Window Closed / Lapsed |