US4422142A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for controlling a plurality of microprocessors
Assignee: Fanuc Corp
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Filing: 1980-06-17
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Granted: 1983-12-20
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Expires: 2000-06-17
Abstract
Abstract A system for controlling a plurality of microprocessors, comprising a common memory which can be selectively switched to exclusive buses which are connected to the plurality of microprocessors, respectively, and a priority control circuit which determines the priority of the microprocessors. According to the system of the present invention, it has a common memory that is selectively connected to the buses, data is transmitted without affecting the operation of the microprocessors on the receiving side, data transfer between the microprocessors having different cycle times is carried out at speeds that are adapted to the cycle times of the individual microprocessors, and the degree of the exclusive use of the bus by the microprocessor is prevented from being reduced when the direct memory access transfer is carried out. Consequently, a system for controlling a plurality of microprocessors having an improved performance is obtained in accordance with the present invention.
Inventors
- 👤 Hajimu Inaba
- 👤 Hideo Miyashita
- 👤 Shoichi Otsuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:58
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/16; G06F13/18; G06F15/00; G06F15/16; G06F15/163; G06F15/167
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
350 words
A system for controlling a plurality of microprocessors comprising: a first and second microprocessor; a first and second bus connected to said first and second microprocessors, respectively; input and output devices connected to said first and second buses, respectively; exclusive memories connected to said first and second buses, respectively; at least one program memory connected to one of said first and second buses; a common memory provided commonly for said first and second microprocessors; address bus branches branched from said first and second buses for transmitting address signals to said common memory; data bus branches branched from said first and second buses for transmitting data to said common memory; switching means provided between said common memory and said bus branches, said switching means being adapted for selectively connecting said common memory through said bus branches to either said first or second bus; and a priority control means for controlling priority of access of said first and second microprocessors to said common memory, the input of said priority control means being connected to said first and second buses for receiving address selection signals, and the output thereof being connected to said first and second microprocessors for sending a wait signal thereto, said priority control means further providing a switch actuating output applied to said switches for switching said switches to determine the priority of access to said common memory between said first and second microprocessors on the basis of the received address selection signals; at least two interruption circuits, one being connected between said first bus and an input terminal of said second microprocessor, and the other being connected between said second bus and an input terminal of said first microprocessor, said interruption circuits providing information from one of the microprocessors to the other of the microprocessors that the microprocessors are ready to access said common memory, thereby preventing simultaneous access to said common memory; whereby the microprocessor which first accesses said common memory obtains the priority and the microprocessor which later accesses said common memory is maintained in the waiting state until the microprocessor obtaining the priority completes the operation.
Claim 2
Independent Claim
350 words
A system for controlling a plurality of microprocessors comprising: a first and second microprocessor; a first and second bus connected to said first and second microprocessors, respectively; input and output devices connected to said first and second buses, respectively; exclusive memories connected to said first and second buses, respectively; at least one program memory connected to one of said first and second buses; a common memory provided commonly for said first and second microprocessors; address bus branches branched from said first and second buses for transmitting address signals to said common memory; data bus branches branched from said first and second buses for transmitting data to said common memory; switching means provided between said common memory and said bus branches, said switching means being adapted for selectively connecting said common memory through said bus branches to either said first or second bus; and a priority control means for controlling priority of access of said first and second microprocessors to said common memory, the input of said priority control means being connected to said first and second buses for receiving address selection signals, and the output thereof being connected to said first and second microprocessors for sending a wait signal thereto, said priority control means further providing a switch actuating output applied to said switches for switching said switches to determine the priority of access to said common memory between said first and second microprocessors on the basis of the received address selection signals; at least two interruption circuits, one being connected between said first bus and an input terminal of said second microprocessor, and the other being connected between said second bus and an input terminal of said first microprocessor, said interruption circuits providing information from one of the microprocessors to the other of the microprocessors that the microprocessors are ready to access said common memory, thereby preventing simultaneous access to said common memory; whereby the microprocessor which first accesses said common memory obtains the priority and the microprocessor which later accesses said common memory is maintained in the waiting state until the microprocessor obtaining the priority completes the operation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-19 | 1987-06-20 | 1987-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-19 | 1991-06-20 | 1991-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-19 | 1995-06-20 | 1995-12-20 | $7700.00 | Window Closed / Lapsed |