Communications system for interconnecting a plurality of asynchronous data processing terminals

Claim 1

A communication system for connecting many asynchronous data processing terminals which are operating at different speeds to a high speed switching and communication network; said system comprising central control circuit means associated with microprocessor means and a plurality of secondary control circuit means; each of said secondary control circuit means being associated with a terminal which is connected to the central control circuit means by a telephone line; the central control circuit means being coupled via a high speed transmission link to the high speed switching and communication center by coupler means and line switch means; means responsive to the microprocessor means for controlling operation of said line switch means; the central control circuit means having central switching means which are capable of taking either a transmitting state or a receiving state; each secondary control circuit means also being able to assume either a receiving state or a transmitting state, means for synchronizing the central control circuit means and the secondary control circuit means for transmitting a sync burst; means for transmitting and receiving bytes of information one-by-one; the central control circuit means is also having addressing means for transmitting an address byte for selecting the secondary control circuit means which is to be interrogated; each of said secondary control circuit means having an address identification circuit means; the central control circuit means having a central sequencing unit means for: (1) operating the switching means of the central control circuit to the transmitting state at the beginning of each interrogation sequence, (2) coupling the synchronization means to the line by way of the said switching means, (3) operating the addressing means, (4) operating the byte transmission means, (5) switching the switching means to the receiving state, and (6) coupling the synchronization means to the line; each of said secondary control circuit means having a secondary sequencing unit for: (a) switching the switching means of the secondary control circuit means between two interrogation sequences to the receiving mode, (b) coupling the synchronization means to the line by way of said switching means, (c) activating the secondary interrogation means in response to the sync burst to couple the address identification circuit to the line means (i) responsive to a negative addressing of a line for causing the isolation of said switching means from the line, and (ii) responsive to a positive addressing of the line for activating a secondary ordering unit to link the byte receiving means to the line; means responsive to the ordering unit for: (1) placing the switching means in the transmitting state, (2) coupling the synchronization means of the secondary control circuit means to the line, (3) coupling the byte transmitting means to the line, (4) switching the switching means to the receiving mode; and (5) means responsive to the synchronization means of the central control circuit means for coupling the byte receiving means to the line in response to the reception of the sync burst from the secondary control circuit means.