Digital signal transmitting system

Claim 2

Apparatus for encoding a digital signal for protection against burst errors, wherein said digital signal occurs as N sequences of data words, comprising input means for receiving said N sequences; encoder means for generating an error correcting word sequence, in each of a plurality n of stages, from said N sequences of data words in a previous stage; delay means for delaying respective words of said N sequences by respective different delay times of (D-d i ) words from an output of said n stages, in each of said n stages, where i is an index identifying an associated one of said n stages and takes on a value i=0 to n-1, and with said N sequences and the n error correcting word sequences at the output of said n stages being delayed with respective total delay times that differ from one another by an integral multiple of a number D of data words; and distributing means forming blocks of the N data word sequences and n error correcting word sequences and distributing such blocks cyclically among a plurality M of transmitting paths; wherein the values of M, N, n, D, and d i are all positive integers which satisfy the conditions that the least common multiple of any two values of (D-d i ) is greater than (N+n-1)D; and for any value of (D-d 1 ), (D-d i ) and M are relatively prime.

Claim 3

Apparatus according to claim 1, wherein M is an integral power of two, and all values of (D-d i ) are odd.

Claim 4

Apparatus according to claim 1, wherein said distributing means includes demultiplexer means for distributing said N data sequences and said n check word sequences among M channels, each such channel including modulator means for modulating the demultiplexed data and error correcting word sequences and transducer means for recording the modulated sequences on a respective track of a record medium.

Claim 5

Apparatus for decoding a received digital signal to correct errors occurring therein during transmission, wherein said digital signal is formed of N sequences of data words and a plurality n of error correcting word sequences, the N data word sequences and n error correcting word sequences being delayed in each of a plurality n of stages by respective different delay times of (D-d i ) words from the output of said n stages, where i is an index identifying an associated one of said n stages and takes on a value i=0 to n-1, each of said N data sequences and n error correcting word sequences being provided with a different total delay time such that the delay times differ from one another by an integral multiple of a number D of data words; and the digital signal is distributed among M receiving channels; wherein M, N, n, D, and d i are all positive integers which satisfy the conditions that the least common multiple of any two values of (D-d i ) is greater than (N+n-1)D; and for any value of (D-d i ), (D-d i ) and M are relatively prime; said apparatus comprising receiving means for cyclially deriving said distributed N data sequences and said n error correcting word sequences from said M channels; a plurality n of stages, each stage including error correction decoder means provided with the N data word sequences and at least a respective one of said n error correcting word sequences from a previous stage, for correcting data words of said N sequences based on at least a respective one of said n error correcting word sequences; delay means provided in each stage for providing a compensatory delay to said N data word sequences and to said n error correcting word sequences to restore said N data word sequences to their relative timing prior to encoding; and output means providing a corrected received digital signal.

Claim 6

Apparatus for decoding a received digital signal to correct errors occurring therein during transmission, wherein said digital signal is formed of N sequences of data words and a plurality n of error correcting word sequences, the N data word sequences and n error correcting word sequences being delayed in each of a plurality n of stages by respective different delay times of (D-d i ) words from the output of said n stages, where i is an index identifying an associated one of said n stages and takes on a value i=0 to n-1, each of said N data sequences and n error correcting word sequences being provided with a different total delay time such that the delay times differ from one another by an integral multiple of a number D of data words; and the digital signal is distributed among M receiving channels; wherein M, N, n, D, and d i are all positive integers which satisfy the conditions that the least common multiple of any two values of (D-d i ) is greater than (N+n-1)D; and for any value of (D-d i ), (D-d i ) and M are relatively prime; said apparatus comprising receiving means for cyclially deriving said distributed N data sequences and said n error correcting word sequences from said M channels; a plurality n of stages, each stage including error correction decoder means provided with the N data word sequences and at least a respective one of said n error correcting word sequences from a previous stage, for correcting data words of said N sequences based on at least a respective one of said n error correcting word sequences; delay means provided in each stage for providing a compensatory delay to said N data word sequences and to said n error correcting word sequences to restore said N data word sequences to their relative timing prior to encoding; and output means providing a corrected received digital signal.

Claim 7

Apparatus for decoding a received digital signal according to claim 4, wherein said output means includes means for detecting any data words having an error uncorrected by said error correction decoder means, and for interpolating between neighboring data words to provide an interpolated data word in substitution for such data word having said uncorrected error.

Claim 8

Apparatus for decoding a received digital signal according to claim 4, wherein said received digital signal is reproduced from M tracks on a record medium, and a reference timing signal is derived from another track on said medium, and wherein said receiving means includes respective time base correction means for each of said M channels responsive to said reference timing signal for removing time base errors in the portion of the digital signal carried on the respective channel.

Claim 11

A method of encoding a digital signal according to claim 7, wherein M is an integral power of two, and all values of (D-d i ) are odd.

Claim 12

A method of encoding a digital signal according to claim 8, wherein N, D, and n are respectively 6, 17, 2; d 0 is 0, and d i is 2.

Claim 13

A method of encoding a digital signal according to claim 7, wherein M, D, and all values of d i are selected to further satisfy the condition that for any two values of i, the remainders of the respective expressions D-d i /M will have different values.

Claim 14

A method of encoding a digital signal according to claim 10, wherein M is selected to be 2 k where k is a positive integer, and n is selected to be no greater than 2 k-1 .