Encoder output pulse detection using two stage shift register and clock oscillator

Claim 1

A pulse detection circuit for detecting output signals of an encoder, which comprises: a first and a second input terminals, each for receiving either one of said encoder output signals containing two successions of pulses being shifted in phase with each other; a first and a second rise-up detectors for detecting the rise-up edges of the pulses being fed to said first and second input terminals; a first and a second fall-down detectors for detecting the fall-down edges of said pulses; a first gate circuit composed of AND gates, each for obtaining a logical product of the output of either one of said first rise-up and fall-down detectors and the signal level at said second input terminal, or for obtaining a logical product of the output of either one of said second rise-up and fall-down detectors and the signal level at said first input terminal; and a second gate circuit composed of OR gates each for obtaining a logical sum of the logical products obtained by said AND gates in said first gate circuit, said second gate circuit comprising a first OR gate which issues a logical sum of the outputs of a part of said AND gates, representing a clockwise rotation of the encoder shaft, and a second OR gate which issues a logical sum of the outputs of a part of the AND gates representing an anti-clockwise rotation of the encoder shaft, and each combination of said first rise-up and fall-down detectors, and of second rise-up and fall-down detectors being constituted by a two stage shift-register, a clock oscillator which feeds a clock pulse to said shift-register, a third gate circuit which receives the outputs of said shift-register and an RS-flip-flop, output terminals of said third gate circuit being connected to said RS-flip-flop which is adjusted to be reset by said clock pulse.