MOSFET Structure and process to form micrometer long source/drain spacing

Claim 1

A method for fabricating a semiconductor integrated circuit structure having at least some field effect transistor devices having a sub-micrometer gate length, comprising: providing a semiconductor substrate; forming a surface isolation pattern in said semiconductor substrate which isolates regions of said semiconductor within said substrate from one another and which regions are designated to contain devices; forming a silicon dioxide layer which is designated to be in part the gate dielectric upon the surface of said substrate having the surface isolation pattern therein; depositing a conductive layer upon said silicon dioxide layer; depositing an insulating layer on said conductive layer; depositing a first silicon nitride layer on said conductive layer; depositing a doped polycrystalline silicon layer upon said silicon nitride layer; depositing a second silicon nitride layer on said polycrystalline silicon layer; selectively etching said second silicon nitride layer and said polycrystalline silicon layer so as to provide remaining portions of said polycrystalline silicon layer having substantially vertical sidewalls, wherein portions of said remaining portions extend across certain of said regions designated to contain devices and onto the surrounding isolation pattern; thermally oxidizing each of said sidewalls to form a silicon dioxide sidewall layer thereon; etching said remaining portions of said polycrystalline silicon layer and overlying second silicon nitride layer; removing the undesired portions of said silicon dioxide sidewall layer; using said sidewall layer as a mask, etch said first silicon nitride layer, and said conductive layer to form the gate electrode of said field effect transistor devices in said conductive layer having the length of said sidewall coating; ion implanting a conductivity imparting impurity adjacent to said gate electrode to form a source/drain element for said field effect devices in said regions designated to contain devices; and forming an insulation layer over said device with openings therein having electrical contacts to the various elements of said devices.

Claim 2

A method for fabricating a semiconductor integrated circuit structure having at least some field effect transistor devices having a sub-micrometer gate length, comprising: providing a semiconductor substrate; forming a surface isolation pattern in said semiconductor substrate which isolates regions of said semiconductor within said substrate from one another and which regions are designated to contain devices; forming a silicon dioxide layer which is designated to be in part the gate dielectric upon the surface of said substrate having the surface isolation pattern therein; depositing a conductive layer upon said silicon dioxide layer; depositing an insulating layer on said conductive layer; depositing a first silicon nitride layer on said conductive layer; depositing a doped polycrystalline silicon layer upon said silicon nitride layer; depositing a second silicon nitride layer on said polycrystalline silicon layer; selectively etching said second silicon nitride layer and said polycrystalline silicon layer so as to provide remaining portions of said polycrystalline silicon layer having substantially vertical sidewalls, wherein portions of said remaining portions extend across certain of said regions designated to contain devices and onto the surrounding isolation pattern; thermally oxidizing each of said sidewalls to form a silicon dioxide sidewall layer thereon; etching said remaining portions of said polycrystalline silicon layer and overlying second silicon nitride layer; removing the undesired portions of said silicon dioxide sidewall layer; using said sidewall layer as a mask, etch said first silicon nitride layer, and said conductive layer to form the gate electrode of said field effect transistor devices in said conductive layer having the length of said sidewall coating; ion implanting a conductivity imparting impurity adjacent to said gate electrode to form a source/drain element for said field effect devices in said regions designated to contain devices; and forming an insulation layer over said device with openings therein having electrical contacts to the various elements of said devices.

Claim 13

A method for fabricating a semiconductor integrated circuit structure having at least some field effect transistor devices having a sub-micrometer gate length, comprising: providing a semiconductor substrate; forming a surface isolation pattern in said semiconductor substrate which isolates regions of said semiconductor within said substrate from one another and which regions are designated to contain devices; forming a silicon dioxide layer which is designated to be in part the gate dielectric upon the surface of said substrate having the surface isolation pattern therein; depositing a conductive layer upon said silicon dioxide layer; depositing an insulating layer on said conductive layer; depositing a first silicon nitride layer on said conductive layer; depositing a doped polycrystalline silicon layer upon said first silicon nitride layer; depositing a second silicon nitride layer on said polycrystalline silicon layer; selectively etching said second silicon nitride layer and said polycrystalline silicon layer so as to provide remaining portions of said polycrystalline silicon layer having substantially vertical sidewalls, wherein portions of said remaining portions extend across certain of said regions designated to contain devices and onto the surrounding isolation pattern; thermally oxidizing each of said sidewalls to form a silicon dioxide sidewall layer thereon, the said portions being so positioned that at least a pair of said sidewall layers extend across said certain of said regions to thereby define the gate region; etching said remaining portions of said polycrystalline silicon layer and overlying silicon nitride layer; removing the undesired portions of said silicon dioxide sidewall layer; forming a resist pattern to cover the desired interconnection pattern of said conductive layer outside of the designated gate electrode over said isolation regions; using said sidewall layer and said resist pattern as a mask, etching said first silicon nitride layer and said conductive layer to form the said gate electrode of said field effect transistor devices and device interconnection pattern in said conductive layer; removing said resist pattern; ion implanting a conductivity imparting impurity adjacent to said gate electrode to form the desired a source/drain element for said field effect devices in said regions designated to contain devices; and forming an insulation layer over said devices with openings therein having electrical contacts to the various elements of said devices.

Claim 14

A method for fabricating a semiconductor integrated circuit structure having at least some field effect transistor devices having a sub-micrometer gate length, comprising: providing a semiconductor substrate; forming a surface isolation pattern in said semiconductor substrate which isolates regions of said semiconductor within said substrate from one another and which regions are designated to contain devices; forming a silicon dioxide layer which is designated to be in part the gate dielectric upon the surface of said substrate having the surface isolation pattern therein; depositing a conductive layer upon said silicon dioxide layer; depositing an insulating layer on said conductive layer; depositing a first silicon nitride layer on said conductive layer; depositing a doped polycrystalline silicon layer upon said first silicon nitride layer; depositing a second silicon nitride layer on said polycrystalline silicon layer; selectively etching said second silicon nitride layer and said polycrystalline silicon layer so as to provide remaining portions of said polycrystalline silicon layer having substantially vertical sidewalls, wherein portions of said remaining portions extend across certain of said regions designated to contain devices and onto the surrounding isolation pattern; thermally oxidizing each of said sidewalls to form a silicon dioxide sidewall layer thereon, the said portions being so positioned that at least a pair of said sidewall layers extend across said certain of said regions to thereby define the gate region; etching said remaining portions of said polycrystalline silicon layer and overlying silicon nitride layer; removing the undesired portions of said silicon dioxide sidewall layer; forming a resist pattern to cover the desired interconnection pattern of said conductive layer outside of the designated gate electrode over said isolation regions; using said sidewall layer and said resist pattern as a mask, etching said first silicon nitride layer and said conductive layer to form the said gate electrode of said field effect transistor devices and device interconnection pattern in said conductive layer; removing said resist pattern; ion implanting a conductivity imparting impurity adjacent to said gate electrode to form the desired a source/drain element for said field effect devices in said regions designated to contain devices; and forming an insulation layer over said devices with openings therein having electrical contacts to the various elements of said devices.

Claim 22

A method for fabricating a semiconductor integrated circuit structure having at least some field effect transistor devices having a sub-micrometer gate length and some field effect transistor devices having gate lengths larger than two times said sub-micrometer gate length, comprising: providing a semiconductor substrate; forming a surface isolation pattern in said semiconductor substrate which isolates regions of said semiconductor within said substrate from one another and which regions are designated to contain devices; forming a silicon dioxide layer which is designated to be in part the gate dielectric upon the surface of said substrate having the surface isolation pattern therein; depositing a first doped polycrystalline silicon layer upon said silicon dioxide layer; depositing an insulating layer on said first polycrystalline silicon layer; depositing a first silicon nitride layer on said first polycrystalline layer; depositing a second doped polycrystalline silicon layer upon said silicon nitride layer; depositing a second silicon nitride layer on said second polycrystalline silicon layer; selectively etching said second silicon nitride layer and said second polycrystalline silicon layer so as to provide remaining portions of said second polycrystalline silicon layer having substantially vertical sidewalls, wherein portions of said remaining portions extend across certain of said regions designated to contain devices and onto the surrounding isolation pattern; thermally oxidizing each of said sidewalls to form a silicon dioxide sidewall layer thereon; the said portions above said regions designated to have said sub-micrometer gate length having one sidewall layer extending across said certain of said regions; the said portions above said regions designated to have said larger than two times said sub-micrometer gate length having a pair of said sidewall layers extending across said certain of said regions; etching said remaining portions of said second polycrystalline silicon layer and overlying second silicon nitride layer; removing the undesired portions of said sidewall layer; forming a resist pattern to cover the desired interconnection pattern of said first polysilicon layer outside of the said designated larger than two times the sub-micrometer gate electrode regions, and the inside portion thereof between said pair of said sidewall layers, and to cover the interconnection pattern of said first polysilicon layer over said surface isolation pattern whereat it is an enlarged size area for contact purposes to said sub-micrometer gate length device; using said sidewall layer and said resist pattern as a mask, etching the first silicon nitride layer and said first polycrystalline silicon layer to form the said gate electrode of said field effect transistor devices and device interconnection pattern in said first polycrystalline silicon layer; removing said resist pattern; ion implanting a conductivity imparting impurity adjacent to said gate electrode to form the desired source/drain element for said field effect devices into said regions designated to contain devices; and forming an insulation layer over said device with openings therein having electrical contacts to the various elements of said devices.

Claim 23

A method for fabricating a semiconductor integrated circuit structure having at least some field effect transistor devices having a sub-micrometer gate length and some field effect transistor devices having gate lengths larger than two times said sub-micrometer gate length, comprising: providing a semiconductor substrate; forming a surface isolation pattern in said semiconductor substrate which isolates regions of said semiconductor within said substrate from one another and which regions are designated to contain devices; forming a silicon dioxide layer which is designated to be in part the gate dielectric upon the surface of said substrate having the surface isolation pattern therein; depositing a first doped polycrystalline silicon layer upon said silicon dioxide layer; depositing an insulating layer on said first polycrystalline silicon layer; depositing a first silicon nitride layer on said first polycrystalline layer; depositing a second doped polycrystalline silicon layer upon said silicon nitride layer; depositing a second silicon nitride layer on said second polycrystalline silicon layer; selectively etching said second silicon nitride layer and said second polycrystalline silicon layer so as to provide remaining portions of said second polycrystalline silicon layer having substantially vertical sidewalls, wherein portions of said remaining portions extend across certain of said regions designated to contain devices and onto the surrounding isolation pattern; thermally oxidizing each of said sidewalls to form a silicon dioxide sidewall layer thereon; the said portions above said regions designated to have said sub-micrometer gate length having one sidewall layer extending across said certain of said regions; the said portions above said regions designated to have said larger than two times said sub-micrometer gate length having a pair of said sidewall layers extending across said certain of said regions; etching said remaining portions of said second polycrystalline silicon layer and overlying second silicon nitride layer; removing the undesired portions of said sidewall layer; forming a resist pattern to cover the desired interconnection pattern of said first polysilicon layer outside of the said designated larger than two times the sub-micrometer gate electrode regions, and the inside portion thereof between said pair of said sidewall layers, and to cover the interconnection pattern of said first polysilicon layer over said surface isolation pattern whereat it is an enlarged size area for contact purposes to said sub-micrometer gate length device; using said sidewall layer and said resist pattern as a mask, etching the first silicon nitride layer and said first polycrystalline silicon layer to form the said gate electrode of said field effect transistor devices and device interconnection pattern in said first polycrystalline silicon layer; removing said resist pattern; ion implanting a conductivity imparting impurity adjacent to said gate electrode to form the desired source/drain element for said field effect devices into said regions designated to contain devices; and forming an insulation layer over said device with openings therein having electrical contacts to the various elements of said devices.