Logic control system for efficient memory to CPU transfers

Claim 2

A logic control system for accomodating the transfer of binary information including CPU instructions from a memory system to a central processing unit (CPU), which comprises: (a) first, seoond, third and fourth register means in electrical communication with said memory system for receiving and storing said binary information, each of said register means being operable to store logic signals representative of a single length word; (b) a first multiplexer connected to the outputs of said first and second register means through a first tristate bus and to said CPU via a first control bus, logic signals on said first tristate bus being provided by said first multiplexer to said CPU in response to a logic selection signal of a given level; (c) a second multiplexer connected to the outputs of said third and fourth register means through a second tristate bus and to said CPU via a second control bus, logic signals on said second tristate bus being provided by said second multiplexer to said CPU in response to said logic selection signal being the complement of said given level; (d) means for providing said logic selection signal to said first and second multiplexers in response to a control signal from said CPU; and (e) means for sequentially providing outputs of said first, second, third and fourth register means onto said first and second tristate busses.

Claim 3

A logic control system in electrical communication with a memory unit and a central processing unit (CPU) by way of a common communication bus, and a local communication bus, comprising: (a) CPU register means responsive to a control signal for receiving binary CPU instruction words and binary procedural words from said memory unit via said local communication bus in response to a CPU request; (b) first, second, third and fourth register means in electrical communication with said CPU register means, each for receiving and storing a single length word; (c) a first multiplexer connected to the outputs of said first and second register means through a first tristate bus and to said CPU via a first control bus, logic signals on said first tristate bus being provided by said first multiplexer to said CPU in response to a logic selection signal of a given level; (d) a second multiplexer connected to the outputs of said third and fourth register means through a second tristate bus and to said CPU via a second control bus, logic signals on said second tristate bus being provided by said second multiplexer to said CPU in response to said logic selection signal being the complement of said given level; (e) means for providing said logic selection signal to said first and second multiplexers in response to a control signal from said CPU; and (f) means for sequentially providing outputs of said first, second, third and fourth register means onto said first and second tristate busses.

Claim 4

A logic control system in electrical communication with a memory unit and a central processing unit (CPU) by way of a common communication bus, and a local communication bus, comprising: (a) CPU register means responsive to a control signal for receiving binary CPU instruction words and binary procedural words from said memory unit via said local communication bus in response to a CPU request; (b) first, second, third and fourth register means in electrical communication with said CPU register means, each for receiving and storing a single length word; (c) a first multiplexer connected to the outputs of said first and second register means through a first tristate bus and to said CPU via a first control bus, logic signals on said first tristate bus being provided by said first multiplexer to said CPU in response to a logic selection signal of a given level; (d) a second multiplexer connected to the outputs of said third and fourth register means through a second tristate bus and to said CPU via a second control bus, logic signals on said second tristate bus being provided by said second multiplexer to said CPU in response to said logic selection signal being the complement of said given level; (e) means for providing said logic selection signal to said first and second multiplexers in response to a control signal from said CPU; and (f) means for sequentially providing outputs of said first, second, third and fourth register means onto said first and second tristate busses.

Claim 5

A logic control system in a data processing system including a central memory unit, a cache memory unit, and a central processing unit (CPU) with a control system, said logic control system which comprises: (a) a system communication bus in electrical communication with said central memory unit and said cache memory unit; (b) a local communication bus in electrical communication with said cache memory unit, said logic control system and said CPU; (c) CPU register means responsive to a control signal and in electrical communication with said local communication bus for receiving both binary CPU instruction words and binary procedural words stored in either said central memory unit or said cache memory unit; (d) a first, second, third and fourth register means in electrical communication with said CPU register means, each for receiving and storing a single length word; (e) a first multiplexer connected to the outputs of said first and second register means through a first tristate bus and to said CPU via a first control bus, logic signals on said first tristate bus being provided by said first multiplexer to said CPU in response to a logic selection signal of a given level; (f) a second multiplexer connected to the outputs of said third and fourth register means through a second tristate bus and to said CPU via a second control bus, logic signals on said second tristate bus being provided by said second multiplexer to said CPU in response to said logic selection signal being the complement of said given level; (g) means for providing said logic selection signal to said first and second multiplexers in response to a control signal from said CPU; and (h) means for sequentially providing outputs of said first, second, third and fourth register means onto said first and second tristate busses.

Claim 6

A logic control system in a data processing system including a central memory unit, a cache memory unit, and a central processing unit (CPU) with a control system, said logic control system which comprises: (a) a system communication bus in electrical communication with said central memory unit and said cache memory unit; (b) a local communication bus in electrical communication with said cache memory unit, said logic control system and said CPU; (c) CPU register means responsive to a control signal and in electrical communication with said local communication bus for receiving both binary CPU instruction words and binary procedural words stored in either said central memory unit or said cache memory unit; (d) a first, second, third and fourth register means in electrical communication with said CPU register means, each for receiving and storing a single length word; (e) a first multiplexer connected to the outputs of said first and second register means through a first tristate bus and to said CPU via a first control bus, logic signals on said first tristate bus being provided by said first multiplexer to said CPU in response to a logic selection signal of a given level; (f) a second multiplexer connected to the outputs of said third and fourth register means through a second tristate bus and to said CPU via a second control bus, logic signals on said second tristate bus being provided by said second multiplexer to said CPU in response to said logic selection signal being the complement of said given level; (g) means for providing said logic selection signal to said first and second multiplexers in response to a control signal from said CPU; and (h) means for sequentially providing outputs of said first, second, third and fourth register means onto said first and second tristate busses.

Claim 7

A logic control system which comprises: (a) a system communication bus that connects a central memory unit to said logic control system: (b) a local communication bus that connects said logic control system and a central processing unit (CPU); (c) CPU register means responsive to a control signal for receiving by way of said local communication bus both binary CPU instruction words and binary procedural words stored in said central memory unit; (d) first, second, third and fourth register means in electrical communication with said CPU register means each for storing and receiving a single length word; (e) a first multiplexer connected to the outputs of said first and second register means through a first tristate bus and to said CPU via a first control bus, logic signals on said first tristate bus being provided by said first multiplexer to said CPU in response to a logic selection signal of a given level; (f) a second multiplexer connected to the outputs of said third and fourth register means through a second tristate bus and to said CPU via a second control bus, logic signals on said second tristate bus being provided by said second multiplexer to said CPU in response to said logic selection signal being the complement of said given level; (g) means for providing said logic selection signal to said first and second multiplexers in response to a control signal from said CPU; and (h) means for sequentially providing outputs of said first, second, third and fourth register means onto said first and second tristate busses.

Claim 8

A logic control system which comprises: (a) a system communication bus that connects a central memory unit to said logic control system: (b) a local communication bus that connects said logic control system and a central processing unit (CPU); (c) CPU register means responsive to a control signal for receiving by way of said local communication bus both binary CPU instruction words and binary procedural words stored in said central memory unit; (d) first, second, third and fourth register means in electrical communication with said CPU register means each for storing and receiving a single length word; (e) a first multiplexer connected to the outputs of said first and second register means through a first tristate bus and to said CPU via a first control bus, logic signals on said first tristate bus being provided by said first multiplexer to said CPU in response to a logic selection signal of a given level; (f) a second multiplexer connected to the outputs of said third and fourth register means through a second tristate bus and to said CPU via a second control bus, logic signals on said second tristate bus being provided by said second multiplexer to said CPU in response to said logic selection signal being the complement of said given level; (g) means for providing said logic selection signal to said first and second multiplexers in response to a control signal from said CPU; and (h) means for sequentially providing outputs of said first, second, third and fourth register means onto said first and second tristate busses.