Nonvolatile MNOS semiconductor memory

Claim 2

A nonvolatile semiconductor memory comprising: a semiconductor body of a first conductivity tube having a surface region, memory cells arrayed in the form of a matrix in the surface region of said body, said each memory cell being comprised of: (i) a metal-nitride-oxide-semiconductor transistor with a first channel provided in the surface region of said body, having a first impurity doped region of a second conductivity type opposite to said first conductivity type, and having a first insulated-gate electrode which is connected to a writing word line; (ii) a metal-insulator-semiconductor transistor with a second channel provided in the surface region of said body, having a second impurity doped region of a second conductivity type, and having a second insulated-gate electrode which is disposed adjacently to the first insulated-gate electrode of said metal-nitride-oxide-semiconductor transistor and is connected to a reading word line, and (iii) wherein said first and second channels are series connected and further comprising means for addressing one specific memory cell of said memory cells by selecting a metal-insulator-semiconductor transistor of said specific memory cell, separate writing lines for each row of said memory array to connect the first insulated-gate electrodes of the memory cells on the same row, and which function as separate row address lines in a writing mode, separate word lines for each row of said memory array to connect the second insulated-gate electrodes of the memory cells on the same row, and which function as separate row lines, means for selectively driving said separate writing lines in a writing mode, means for selectively driving said separate word lines in a reading mode and in said writing mode, and means for applying in an erasing mode an erasing voltage V E to said body while grounding said first and second insulated-gates of the memory cell and holding said first and second impurity doped regions of the memory cell in a floating condition.

Claim 3

A nonvolatile semiconductor memory comprising: a semiconductor body of a first conductivity type having a surface region, memory cells arrayed in the form of a matrix in the surface of said body, said each memory cell being comprised of: (i) a metal-nitride-oxide-semiconductor transistor with a first channel provided in the surface region of said body, having a first impurity doped region of a second conductivity type opposite to said first conductivity type, and having a first insulated-gate electrode which is connected to a writing word line; (ii) a metal-insulator-semiconductor transistor with a second channel provided in the surface region of said body, having a second impurity doped region of a second conductivity type, and having a second insulated-gate electrode which is disposed adjacently to the first insulated-gate electrode of said metal-nitride-oxide-semiconductor transistor and is connected to a reading word line; and (iii) wherein said first and second channels are series connected and further comprising means for applying in an erasing mode an erasing voltage V E to said body while grounding said first and second insulated-gates of the memory cell and holding said first and second impurity doped regions of the memory cell in a floating condition.

Claim 4

A nonvolatile semiconductor memory comprising: a semiconductor body of a first conductivity type having a surface region, memory cells arrayed in the form of a matrix in the surface of said body, said each memory cell being comprised of: (i) a metal-nitride-oxide-semiconductor transistor with a first channel provided in the surface region of said body, having a first impurity doped region of a second conductivity type opposite to said first conductivity type, and having a first insulated-gate electrode which is connected to a writing word line; (ii) a metal-insulator-semiconductor transistor with a second channel provided in the surface region of said body, having a second impurity doped region of a second conductivity type, and having a second insulated-gate electrode which is disposed adjacently to the first insulated-gate electrode of said metal-nitride-oxide-semiconductor transistor and is connected to a reading word line; and (iii) wherein said first and second channels are series connected and further comprising means for applying in an erasing mode an erasing voltage V E to said body while grounding said first and second insulated-gates of the memory cell and holding said first and second impurity doped regions of the memory cell in a floating condition.

Claim 5

A nonvolatile semiconductor memory according to claim 1, further comprising means for setting in a reading mode the first insulated-gate electrode of the memory cell at a certain fixed potential between a threshold voltage of said metal-nitride-oxide-semiconductor transistor at a written state and a threshold voltage at an erased state.

Claim 6

A nonvolatile semiconductor memory according to claim 3, wherein said first and second impurity doped regions have N-type conductivity.

Claim 7

A nonvolatile semiconductor memory according to claim 4 wherein the first insulated-gate electrode of the memory cell is set substantially at a ground potential at a reading mode.

Claim 8

A nonvolatile semiconductor memory according to claim 1, further comprising means for applying in a writing mode a writing voltage Vp to one selected writing word line, and means for setting up in a writing mode a potential Vc of a channel under a first insulated-gate electrode of one specific memory cell so as to produce a difference voltage (Vp-Vc) larger than a voltage necessary for writing on said metal-nitride-oxide-semiconductor transistor to occur in a predetermined write time.

Claim 9

A nonvolatile semiconductor memory according to claim 1, 3, 4, 5, 6 or 2, wherein a third impurity doped region of said second conductivity type is provided, in said each memory cell in that part of the surface region of said body in which said first and second insulated-gate electrodes are adjacent.

Claim 10

A nonvolatile semiconductor memory according to claim 1, 3, 4, 5, 6 or 2 wherein said first insulated-gate electrode and said second insulated-gate electrode in said each memory cell overlap through an insulating layer in an adjacent portion.

Claim 11

A nonvolatile semiconductor memory according to claim 1, wherein one of said first and second impurity doped regions in said each memory cell is connected to a data line.

Claim 12

A nonvolatile semiconductor memory according to claim 9, wherein said data line is made of aluminum.

Claim 13

A nonvolatile semiconductor memory according to claim 1, wherein said first and second insulated-gate electrodes are made of polycrystalline silicon.

Claim 14

A nonvolatile semiconductor memory according to claim 11 wherein said first and second insulated-gate electrodes are respectively provided integrally with said writing word line and said reading word line each of which is made of polycrystalline silicon.

Claim 15

A nonvolatile semiconductor memory according to claim 1 wherein said metal-insulator-semiconductor transistor is a metal-oxide-semiconductor transistor.

Claim 16

A nonvolatile semiconductor memory comprising: a plurality of memory cells which are arrayed in the form of a matrix in a surface region of a semiconductor body having a first conductivity type, said each memory cell being comprised of: (i) a first impurity doped region having a second conductivity type opposite to said first conductivity type, and disposed in the surface region of said body; (ii) a second impurity doped region having said second conductivity type, and disposed in the surface region of said body apart from said first impurity doped region; (iii) a first gate electrode disposed adjacently to said first impurity doped region, and disposed on a first portion of a surface region between said first and second impurity doped regions through a first gate insulating film which consists of a silicon dioxide layer and silicon nitride thereon with a first channel thereunder; (iv) a second gate electrode disposed adjacently to said second impurity doped region and disposed on a second portion of the surface region between said first and second impurity doped regions through a second gate insulating film with a second channel thereunder, whereby a series connection of said first and second channels of a metal-nitride-oxide-semiconductor transistor which has said first gate electrode and a metal-insulator-semiconductor transistor which has said second gate electrode is provided, and writing lines which connect the first insulated-gate electrodes of the memory cells on the same row, and funcetion as row address lines in a writing mode, word lines which connect the second insulated-gate electrodes of the memory cells on the same row, and function as row address lines, data lines which connect the second impurity doped regions of the memory cells on the same column, a common line which connects the first impurity doped regions of all the memory cells, means for setting said common line at a ground potential in a reading mode, and applying a storage holding voltage to said common line in a writing mode, and holding said common line in open state in an erasing mode, means for applying a reading voltage to a selected data line in a reading mode, and setting a selected datat line at a ground potential in a writing mode, and holding non-selected data lines in open state in said writing mode, and holding all the data lines in open state in an erasing mode, means for setting all the writing lines substantially at a ground potential in reading and erasing modes, and applying a writing voltage to a selected writing line in a writing mode, and means for applying a reading voltage to a selected word line in reading and writing modes, and setting all the word lines at a ground potential in an erasing mode.

Claim 17

A nonvolatile semiconductor memory comprising: a plurality of memory cells which are arrayed in the form of a matrix in a surface region of a semiconductor body having a first conductivity type, said each memory cell being comprised of: (i) a first impurity doped region having a second conductivity type opposite to said first conductivity type, and disposed in the surface region of said body; (ii) a second impurity doped region having said second conductivity type, and disposed in the surface region of said body apart from said first impurity doped region; (iii) a first gate electrode disposed adjacently to said first impurity doped region, and disposed on a first portion of a surface region between said first and second impurity doped regions through a first gate insulating film which consists of a silicon dioxide layer and silicon nitride thereon with a first channel thereunder; (iv) a second gate electrode disposed adjacently to said second impurity doped region and disposed on a second portion of the surface region between said first and second impurity doped regions through a second gate insulating film with a second channel thereunder, whereby a series connection of said first and second channels of a metal-nitride-oxide-semiconductor transistor which has said first gate electrode and a metal-insulator-semiconductor transistor which has said second gate electrode is provided, and writing lines which connect the first insulated-gate electrodes of the memory cells on the same row, and funcetion as row address lines in a writing mode, word lines which connect the second insulated-gate electrodes of the memory cells on the same row, and function as row address lines, data lines which connect the second impurity doped regions of the memory cells on the same column, a common line which connects the first impurity doped regions of all the memory cells, means for setting said common line at a ground potential in a reading mode, and applying a storage holding voltage to said common line in a writing mode, and holding said common line in open state in an erasing mode, means for applying a reading voltage to a selected data line in a reading mode, and setting a selected datat line at a ground potential in a writing mode, and holding non-selected data lines in open state in said writing mode, and holding all the data lines in open state in an erasing mode, means for setting all the writing lines substantially at a ground potential in reading and erasing modes, and applying a writing voltage to a selected writing line in a writing mode, and means for applying a reading voltage to a selected word line in reading and writing modes, and setting all the word lines at a ground potential in an erasing mode.

Claim 18

A nonvolatile semiconductor memory comprising: a plurality of memory cells which are arrayed in the form of a matrix in a surface region of a semiconductor body having a first conductivity type, said each memory cell being comprised of: (i) a first impurity doped region having a second conductivity type opposite to said first conductivity type, and disposed in the surface region of said body; (ii) a second impurity doped region having said second conductivity type, and disposed in the surface region of said body apart from said first impurity doped region; (iii) a first gate electrode disposed adjacently to said first impurity doped region, and disposed on a first portion of a surface region between said first and second impurity doped regions through a first gate insulating film which consists of a silicon dioxide layer and silicon nitride layer thereon with a first channel thereunder; (iv) a second gate electrode disposed adjacently to said second impurity doped region and disposed on a second portion of the surface region between said first and second impurity doped regions through a second gate insulating film with a second channel thereunder, whereby a series connection of said first and second channels of a metal-nitride-oxide-semiconductor transistor which has said first gate electrode and a metal-insulator-semiconductor transistor which has said second gate electrode is provided, and writing lines which connect the first insulated-gate electrodes of the memory cells on the same row, and function as row address lines in a writing mode, word lines which connect the second insulated-gate electrodes of the memory cells on the same row, and function as row address lines, data lines which connect the second impurity doped regions of the memory cells on the same column, a common line which connects the first impurity doped regions of all the memory cells, means for setting a selected data line substantially at a ground potential and holding non-selected data lines in open state in a writing mode, means for applying a storage holding voltage to said common line and a writing voltage to a selected line and an addressing voltage to a selected word line in a writing mode.

Claim 19

A nonvolatile semiconductor memory comprising: a plurality of memory cells which are arrayed in the form of a matrix in a surface region of a semiconductor body having a first conductivity type, said each memory cell being comprised of: (i) a first impurity doped region having a second conductivity type opposite to said first conductivity type, and disposed in the surface region of said body; (ii) a second impurity doped region having said second conductivity type, and disposed in the surface region of said body apart from said first impurity doped region; (iii) a first gate electrode disposed adjacently to said first impurity doped region, and disposed on a first portion of a surface region between said first and second impurity doped regions through a first gate insulating film which consists of a silicon dioxide layer and silicon nitride layer thereon with a first channel thereunder; (iv) a second gate electrode disposed adjacently to said second impurity doped region and disposed on a second portion of the surface region between said first and second impurity doped regions through a second gate insulating film with a second channel thereunder, whereby a series connection of said first and second channels of a metal-nitride-oxide-semiconductor transistor which has said first gate electrode and a metal-insulator-semiconductor transistor which has said second gate electrode is provided, and writing lines which connect the first insulated-gate electrodes of the memory cells on the same row, and function as row address lines in a writing mode, word lines which connect the second insulated-gate electrodes of the memory cells on the same row, and function as row address lines, data lines which connect the second impurity doped regions of the memory cells on the same column, a common line which connects the first impurity doped regions of all the memory cells, means for setting a selected data line substantially at a ground potential and holding non-selected data lines in open state in a writing mode, means for applying a storage holding voltage to said common line and a writing voltage to a selected line and an addressing voltage to a selected word line in a writing mode.

Claim 20

A nonvolatile semiconductor memory comprising: a plurality of memory cells which are arrayed in the form of a matrix in a surface region of a semiconductor body having a first conductivity type, said each memory cell being comprised of: (i) a first impurity doped region having a second conductivity type opposite to said first conductivity type, and disposed in the surface region of said body; (ii) a second impurity doped region having said second conductivity type, and disposed in the surface region of said body apart from said first impurity doped region; (iii) a first gate electrode disposed adjacently to said first impurity doped region, and disposed on a first portion of a surface region between said first and second impurity doped regions through a first gate insulating film which consists of a silicon dioxide layer and silicon nitride layer thereon with a first channel thereunder; (iv) a second gate electrode disposed adjacently to said second impurity doped region and disposed on a second portion of the surface region between said first and second impurity doped regions through a second gate insulating film with a second channel thereunder, whereby a series connection of said first and second channels of a metal-nitride-oxide-semiconductor transistor which has said first gate electrode and a metal-insulator-semiconductor transistor which has said second gate electrode is provided, and writing lines which connect the first insulated-gate electrodes of the memory cells on the same row, and function as row address lines in a writing mode, word lines which connect the second insulated-gate electrodes of the memory cells on the same row, and function as row address lines, data lines which connect the first impurity doped regions of the memory cells on the same column, and a common line which connects the first impurity doped regions of all the memory cells, means for holding said common line and all the data lines in open state in an erasing mode, means for setting all the writing lines and all the word lines substantially at a ground potential in an erasing mode, means for applying an erasing voltage to said body in an erasing mode.

Claim 21

A nonvolatile semiconductor memory comprising: a plurality of memory cells which are arrayed in the form of a matrix in a surface region of a semiconductor body having a first conductivity type, said each memory cell being comprised of: (i) a first impurity doped region having a second conductivity type opposite to said first conductivity type, and disposed in the surface region of said body; (ii) a second impurity doped region having said second conductivity type, and disposed in the surface region of said body apart from said first impurity doped region; (iii) a first gate electrode disposed adjacently to said first impurity doped region, and disposed on a first portion of a surface region between said first and second impurity doped regions through a first gate insulating film which consists of a silicon dioxide layer and silicon nitride layer thereon with a first channel thereunder; (iv) a second gate electrode disposed adjacently to said second impurity doped region and disposed on a second portion of the surface region between said first and second impurity doped regions through a second gate insulating film with a second channel thereunder, whereby a series connection of said first and second channels of a metal-nitride-oxide-semiconductor transistor which has said first gate electrode and a metal-insulator-semiconductor transistor which has said second gate electrode is provided, and writing lines which connect the first insulated-gate electrodes of the memory cells on the same row, and function as row address lines in a writing mode, word lines which connect the second insulated-gate electrodes of the memory cells on the same row, and function as row address lines, data lines which connect the first impurity doped regions of the memory cells on the same column, and a common line which connects the first impurity doped regions of all the memory cells, means for holding said common line and all the data lines in open state in an erasing mode, means for setting all the writing lines and all the word lines substantially at a ground potential in an erasing mode, means for applying an erasing voltage to said body in an erasing mode.

Claim 22

A nonvolatile semiconductor memory comprising: a plurality of memory cells which are arrayed in the form of a matrix in a surface region of a semiconductor body having a first conductivity type, said each memory cell being comprised of: (i) a first impurity doped region having a second conductivity type opposite to said first conductivity type, and disposed in the surface region of said body; (ii) a second impurity doped region having said second conductivity type, and disposed in the surface region of said body apart from said first impurity doped region; (iii) a first gate electrode disposed adjacently to said first impurity doped region, and disposed on a first portion of a surface region between said first and second impurity doped regions through a first gate insulating film which consists of a silicon dioxide layer and silicon nitride layer thereon with a first channel thereunder; (iv) a second gate electrode disposed adjacently to said impurity doped region and disposed on a second portion of the surface region between said first and second impurity doped regions through a second gate insulating film with a second channel thereunder, whereby a series connection of said first and second channels of a metal-nitride-oxide-semiconductor transistor which has said first gate electrode and a metal-insulator-semiconductor transistor which has said second gate electrode is provided, separate writing lines for each row of said memory array to connect the first insulated-gate electrodes of the memory cells on the same row, and which function as row address lines in a writing mode, separate word lines for each row of said memory array to connect the second insulated-gate electrodes of the memory cells on the same row, and which function as row address lines, data lines which connect either of the first and second impurity doped regions of the memory cells on the same column, means for selectively driving said separate writing lines in a writing mode, means for selectively driving said separate word lines in a reading mode and in said writing mode, means for applying a reading voltage to a selected word line in a reading mode, and means for setting a selected writing line at a certain fixed potential smaller than said reading voltage in a reading mode, said nonvolatile semiconductor memory further comprising means for setting said selected writing line and said selected word line substantially at a ground potential in an erasing mode.

Claim 23

A nonvolatile semiconductor memory comprising: a plurality of memory cells which are arrayed in the form of a matrix in a surface region of a semiconductor body having a first conductivity type, said each memory cell being comprised of: (i) a first impurity doped region having a second conductivity type opposite to said first conductivity type, and disposed in the surface region of said body; (ii) a second impurity doped region having said second conductivity type, and disposed in the surface region of said body apart from said first impurity doped region; (iii) a first gate electrode disposed adjacently to said first impurity doped region, and disposed on a first portion of a surface region between said first and second impurity doped regions through a first gate insulating film which consists of a silicon dioxide layer and silicon nitride layer thereon with a first channel thereunder; (iv) a second gate electrode disposed adjacently to said impurity doped region and disposed on a second portion of the surface region between said first and second impurity doped regions through a second gate insulating film with a second channel thereunder, whereby a series connection of said first and second channels of a metal-nitride-oxide-semiconductor transistor which has said first gate electrode and a metal-insulator-semiconductor transistor which has said second gate electrode is provided, separate writing lines for each row of said memory array to connect the first insulated-gate electrodes of the memory cells on the same row, and which function as row address lines in a writing mode, separate word lines for each row of said memory array to connect the second insulated-gate electrodes of the memory cells on the same row, and which function as row address lines, data lines which connect either of the first and second impurity doped regions of the memory cells on the same column, means for selectively driving said separate writing lines in a writing mode, means for selectively driving said separate word lines in a reading mode and in said writing mode, means for applying a reading voltage to a selected word line in a reading mode, and means for setting a selected writing line at a certain fixed potential smaller than said reading voltage in a reading mode, said nonvolatile semiconductor memory further comprising means for setting said selected writing line and said selected word line substantially at a ground potential in an erasing mode.

Claim 24

A nonvolatile semiconductor memory comprising: a plurality of memory cells which are arrayed in the form of a matrix in a surface region of a semiconductor body having a first conductivity type, said each memory cell being comprised of: (i) a first impurity doped region having a second conductivity type opposite to said first conductivity type, and disposed in the surface region of said body; (ii) a second impurity doped region having said second conductivity type, and disposed in the surface region of said body apart from said first impurity doped region; (iii) a first gate electrode disposed adjacently to said first impurity doped region, and disposed on a first portion of a surface region between said first and second impurity doped regions through a first gate insulating film which consists of a silicon dioxide layer and silicon nitride layer thereon with a first channel thereunder; (iv) a second gate electrode disposed adjacently to said impurity doped region and disposed on a second portion of the surface region between said first and second impurity doped regions through a second gate insulating film with a second channel thereunder, whereby a series connection of said first and second channels of a metal-nitride-oxide-semiconductor transistor which has said first gate electrode and a metal-insulator-semiconductor transistor which has said second gate electrode is provided, separate writing lines for each row of said memory array to connect the first insulated-gate electrodes of the memory cells on the same row, and which function as row address lines in a writing mode, separate word lines for each row of said memory array to connect the second insulated-gate electrodes of the memory cells on the same row, and which function as row address lines, data lines which connect either of the first and second impurity doped regions of the memory cells on the same column, means for selectively driving said separate writing lines in a writing mode, means for selectively driving said separate word lines in a reading mode and in said writing mode, means for applying a reading voltage to a selected word line in a reading mode, and means for setting a selected writing line at a certain fixed potential smaller than said reading voltage in a reading mode, said nonvolatile semiconductor memory further comprising means for applying a reading voltage to a selected data line in a reading mode and setting said data line substantially at a ground potential in a writing mode and holding said data line in open state in an erasing mode.

Claim 25

A nonvolatile semiconductor memory comprising: a plurality of memory cells which are arrayed in the form of a matrix in a surface region of a semiconductor body having a first conductivity type, said each memory cell being comprised of: (i) a first impurity doped region having a second conductivity type opposite to said first conductivity type, and disposed in the surface region of said body; (ii) a second impurity doped region having said second conductivity type, and disposed in the surface region of said body apart from said first impurity doped region; (iii) a first gate electrode disposed adjacently to said first impurity doped region, and disposed on a first portion of a surface region between said first and second impurity doped regions through a first gate insulating film which consists of a silicon dioxide layer and silicon nitride layer thereon with a first channel thereunder; (iv) a second gate electrode disposed adjacently to said impurity doped region and disposed on a second portion of the surface region between said first and second impurity doped regions through a second gate insulating film with a second channel thereunder, whereby a series connection of said first and second channels of a metal-nitride-oxide-semiconductor transistor which has said first gate electrode and a metal-insulator-semiconductor transistor which has said second gate electrode is provided, separate writing lines for each row of said memory array to connect the first insulated-gate electrodes of the memory cells on the same row, and which function as row address lines in a writing mode, separate word lines for each row of said memory array to connect the second insulated-gate electrodes of the memory cells on the same row, and which function as row address lines, data lines which connect either of the first and second impurity doped regions of the memory cells on the same column, means for selectively driving said separate writing lines in a writing mode, means for selectively driving said separate word lines in a reading mode and in said writing mode, means for applying a reading voltage to a selected word line in a reading mode, and means for setting a selected writing line at a certain fixed potential smaller than said reading voltage in a reading mode, said nonvolatile semiconductor memory further comprising means for applying a reading voltage to a selected data line in a reading mode and setting said data line substantially at a ground potential in a writing mode and holding said data line in open state in an erasing mode.

Claim 26

A nonvolatile semiconductor memory comprising: a plurality of memory cells which are arrayed in the form of a matrix in a surface region of a semiconductor body having a first conductivity type, said each memory cell being comprised of: (i) a first impurity doped region having a second conductivity type opposite to said first conductivity type, and disposed in the surface region of said body; (ii) a second impurity doped region having said second conductivity type, and disposed in the surface region of said body apart from said first impurity doped region; (iii) a first gate electrode disposed adjacently to said first impurity doped region, and disposed on a first portion of a surface region between said first and second impurity doped regions through a first gate insulating film which consists of a silicon dioxide layer and silicon nitride layer thereon with a first channel thereunder; (iv) a second gate electrode disposed adjacently to said second impurity doped region and disposed on a second portion of the surface region between said first and second impurity doped regions through a second gate insulating filrm with a second channel thereunder, whereby a series connection of said first and second channels of a metal-nitride-oxide-semiconductor transistor which has said first gate electrode and a metal-insulator-semiconductor transistor which has said second gate electrode is provided, and switching means for switching at least two conditions, the first of which is the condition applying a storage holding voltage to the first impurity doped region of said memory cell, and the second of which is the condition setting the first impurity doped region of said memory cell substantially at a ground potential.

Claim 27

A nonvolatile semiconductor memory comprising: a plurality of memory cells which are arrayed in the form of a matrix in a surface region of a semiconductor body having a first conductivity type, said each memory cell being comprised of: (i) a first impurity doped region having a second conductivity type opposite to said first conductivity type, and disposed in the surface region of said body; (ii) a second impurity doped region having said second conductivity type, and disposed in the surface region of said body apart from said first impurity doped region; (iii) a first gate electrode disposed adjacently to said first impurity doped region, and disposed on a first portion of a surface region between said first and second impurity doped regions through a first gate insulating film which consists of a silicon dioxide layer and silicon nitride layer thereon with a first channel thereunder; (iv) a second gate electrode disposed adjacently to said second impurity doped region and disposed on a second portion of the surface region between said first and second impurity doped regions through a second gate insulating filrm with a second channel thereunder, whereby a series connection of said first and second channels of a metal-nitride-oxide-semiconductor transistor which has said first gate electrode and a metal-insulator-semiconductor transistor which has said second gate electrode is provided, and switching means for switching at least two conditions, the first of which is the condition applying a storage holding voltage to the first impurity doped region of said memory cell, and the second of which is the condition setting the first impurity doped region of said memory cell substantially at a ground potential.

Claim 28

A nonvolatile semiconductor memory according to claim 19, wherein said switching means switches three conditions, the third of which is the condition holding the first impurity doped region of said memory cell in a floating condition.