Control signal-multiplexing circuit

Claim 2

A control signal-multiplexing circuit which comprises: a multiplexer having a multiplexing signal for scanning and multiplexing by time division control signals selected from a plurality of channels to produce a first multiplexed control signal; and a control signal-converting circuit for receiving said first multiplexed control signal, detecting whether the logic level of the control signals of the respective channels included in said first multiplexed control signal has risen or not, and in the event a rise is detected, generating a second multiplexed control signal formed of a rising pulse, and delivering said second multiplexed control signal to a first control line.

Claim 3

The control signal-multiplexing circuit according to claim 1, wherein said multiplexer comprises a plurality of clocked inverters which are provided for the respective channels, and which are scanned and driven by the multiplexing signal.

Claim 4

The control signal-multiplexing circuit according to claim 1, wherein said control signal-converting circuit comprises: a first shift register for delaying an output signal from the multiplexer by one scanning period of the multiplexing signal; and a first logic circuit for comparing the logic level of of the control signals included in said first multiplexed control signal with that of an output signal from the first shift register, detecting whether the logic level of the control signals included in said first multiplexed control signal has risen or not, and, in the event a rise is detected, generating said second multiplexed control signal formed of said rising pulse, and delivering said second multiplexed control signal to said first control line.

Claim 5

The control signal-multiplexing circuit according to claim 3, wherein said first logic circuit comprises: an inverter supplied with the output signal from the multiplexer; and a NOR gate having a first terminal supplied with the output signal from said inverter, and a second terminal supplied with the output signal from said first shift register.

Claim 6

The control signal multiplexing circuit according to claim 3, wherein said control signal-converting circuit further comprises a second logic circuit, connected to the output terminal of the first logic circuit for maintaining the logic level of the respective channels of said second multiplexed control signal at a high logic level after the respective channels has risen to the high logic level, and delivering a state-holding pulse to a second control line.

Claim 7

The control signal-multiplexing circuit according to claim 5, wherein said second logic circuit comprises: a first NOR gate having a first terminal supplied with an output signal from the first logic circuit; a second NOR gate having a first terminal supplied with an output signal from the first NOR gate, and a second terminal supplied with a reset signal for resetting the logic level of the respective channels of said second multiplexed control signal at a low logic level; and a second shift register which delays the output signal from the second NOR gate by one scanning period of the multiplexing signal, and an output signal supplied to the second terminal of the first NOR gate and to the second control line.

Claim 8

The control signal-multiplexing circuit according to any one of claims 3 to 5, wherein said first shift register is of the dynamic type.

Claim 9

The control signal-multiplexing circuit according to claim 6, wherein said first and second shift registers are of the dynamic type.

Claim 10

The control signal-multiplexing circuit according to claim 1, wherein said control signal-converting circuit comprises: a data-selecting circuit for selecting said first multiplexed control signal from the multiplexer; a first shift register for delaying a selected first multiplexed control signal from the data-selecting circuit by one scanning period of the multiplexing signal; and a first logic circuit for comparing the logic level of said selected first multiplexed control signal with that of an output signal from the first shift register, detecting whether the logic level of the selected first multiplexed control signal has risen or not, and, in the event a rise is detected, generating said second multiplexed control signal formed of said rising pulse, and delivering said second multiplexed control signal to the first control line.

Claim 11

The control signal-multiplexing circuit according to claim 9, wherein said data-selecting circuit includes: a first clocked inverter actuated by a clock signal φ A having the same pulse width as one scanning period of the multiplexing signal and issued for a period of time corresponding to a prescribed chattering-suppressing period, said first clocked inverter being supplied with said first multiplexed control signal from the multiplexer; a second clocked inverter supplied with said output signal from the first shift register and actuated by a clock signal φ A having a phase opposite to that of the clock signal φ A ; and an inverter supplied with the output signal from the first clocked inverter and the output signal from the second clocked inverter, and having an output signal supplied to the first shift register; and wherein said first logic circuit includes: a NOR gate having a first terminal connected to the output terminals of the first and second clocked inverters of the data-selecting circuit, and a second terminal connected to the output terminal of the first shift register.

Claim 12

The control signal-multiplexing circuit according to claim 9, wherein said data-selecting circuit includes: a first AND gate having a first terminal supplied with said first multiplexed control signal from the multiplexer, and a second terminal supplied with a clock signal φ A having the same pulse width as one scanning period of the multiplexing signal and issued for a period of time corresponding to a prescribed chattering-suppressing period; a second AND gate having a first terminal supplied with said output signal from the first shift register and a second terminal is supplied with the clock pulse φ A through the inverter; and an OR gate supplied with output signals from the first and second AND gates, and having an output signal supplied to the first shift register.

Claim 13

The control signal-multiplexing circuit according to claim 9, wherein said control signal-converting circuit further comprises a second logic circuit, connected to the output terminal of the first logic circuit for maintaining the logic level of the respective channels of said second multiplexed control signal at a high logic level after the respective channels have reached the high logic level, and producing a state-holding pulse to a second control line.

Claim 14

The control signal-multiplexing circuit according to claim 12, wherein said second logic circuit includes: a first NOR gate having a first terminal supplied with an output signal from the first logic circuit; a second NOR gate having a first terminal supplied with an output signal from the first NOR gate, and a second terminal supplied with a reset signal for resetting the logic level of the respective channels of said second multiplexed control signal at a low logic level; and a second shift register which delays the output signal from the second NOR gate by one scanning period of the multiplexing signal, and an output signal supplied to the second control line through the second terminal of the first NOR gate.

Claim 15

The control signal-multiplexing circuit according to any one of claims 9 to 12, wherein the first shift register is of the dynamic type.

Claim 16

The control signal-multiplexing circuit according to claim 13, wherein the first and second shift registers are of the dynamic type.

Claim 17

The control signal-multiplexing circuit according to claim 1, wherein the multiplexer and control signal-converting circuit are integrated.