Phase locked loop frequency synthesizer including fractional digital frequency divider

Claim 2

In a fractional frequency synthesizer comprising a voltage-controlled oscillator (VCO) for generating an output signal S VCO of frequency F VCO , dividing means for dividing F VCO in division cycles with each division cycle consisting of the division of F VCO by N, Y times, and by (N+M), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , where the division ratio is ##EQU3## and N, Y, M and Z are integers, a reference signal generating means for generating a reference signal S R of frequency F R , and phase detector means responsive to S N and S R to produce an output signal whose amplitude is representative of the phase therebetween; a control circuit comprising: means for detecting and averaging the output signals from said phase detector means during each division of F VCO in each division cycle to produce a d.c. control signal whose amplitude is substantially constant and proportional to the average of the amplitudes of the detected output signals over each division cycle; said VCO responsive to said d.c. control signal to generate an output signal S VCO whose divided frequency F N =F R .

Claim 3

In a fractional frequency synthesizer comprising a voltage-controlled oscillator (VCO) for generating an output signal S VCO of frequency F VCO , dividing means for dividing F VCO in division cycles with each division cycle consisting of the division of F VCO by N, Y times, and by (N+M), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , and where Y, M and Z are integers, a reference signal generating means for generating a reference signal S R of frequency F R , and phase detector means responsive to S N and S R to produce an output signal whose amplitude is representative of the phase therebetween; a control circuit comprising: (Y+Z) sample and hold circuits each responsive, when enabled, to sample and hold the output signal of said phase detector; first means responsive to said divided output signal S N to successively and cyclically enable each of said sample and hold circuits to sample and hold the output signal of said phase detector during one of said divisions; and second means for summing and smoothing the contents of said sample and hold circuits each division cycle to produce a control signal of substantially constant amplitude for any given values of N, Y, M and Z; said VCO responsive to said control signal to supply an output signal to said dividing means having a substantially constant frequency of a value such that F N =F R .

Claim 4

In a fractional frequency synthesizer comprising a voltage-controlled oscillator (VCO) for generating an output signal S VCO of frequency F VCO , dividing means for dividing F VCO in division cycles with each division cycle consisting of the division of F VCO by N, Y times, and by (N+M), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , and where Y, M and Z are integers, a reference signal generating means for generating a reference signal S R of frequency F R , and phase detector means responsive to S N and S R to produce an output signal whose amplitude is representative of the phase therebetween; a control circuit comprising: (Y+Z) sample and hold circuits each responsive, when enabled, to sample and hold the output signal of said phase detector; first means responsive to said divided output signal S N to successively and cyclically enable each of said sample and hold circuits to sample and hold the output signal of said phase detector during one of said divisions; and second means for summing and smoothing the contents of said sample and hold circuits each division cycle to produce a control signal of substantially constant amplitude for any given values of N, Y, M and Z; said VCO responsive to said control signal to supply an output signal to said dividing means having a substantially constant frequency of a value such that F N =F R .

Claim 5

A fractional frequency synthesizer comprising: a voltage-controlled oscillator (VCO) for generating an output signal S VCO of frequency F VCO ; dividing means for dividing F VCO by division cycles with each division cycle consisting of dividing F VCO by N, Y times, and by (N+1), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , and where Y and Z are integers; first means for generating a reference signal S R of frequency F R ; phase detector means responsive to S N and S R to produce an output signal whose amplitude is representative of the phase therebetween; and means for detecting and averaging the output signal of said phase detector means during each division of F VCO in each division cycle to produce a d.c. control signal whose amplitude is substantially constant and proportional to the average of the amplitudes of the detected output signals; said VCO responsive to said d.c. control signal to generate an output signal S VCO whose divided frequency F N =F R .

Claim 6

A fractional frequency synthesizer comprising: a voltage-controlled oscillator (VCO) for generating an output signal S VCO of frequency F VCO ; dividing means for dividing F VCO by division cycles with each division cycle consisting of dividing F VCO by N, Y times, and by (N+1), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , and where Y and Z are integers; first means for generating a reference signal S R of frequency F R ; phase detector means responsive to S N and S R to produce an output signal whose amplitude is representative of the phase therebetween; and means for detecting and averaging the output signal of said phase detector means during each division of F VCO in each division cycle to produce a d.c. control signal whose amplitude is substantially constant and proportional to the average of the amplitudes of the detected output signals; said VCO responsive to said d.c. control signal to generate an output signal S VCO whose divided frequency F N =F R .

Claim 7

A fractional frequency synthesizer comprising: a voltage-controlled oscillator (VCO) for generating an output signal S VCO of frequency F VCO ; dividing means for dividing F VCO by division cycles with each division cycle consisting of the division of F VCO by N, Y times, and by (N+1), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , and where Y and Z are integers; first means for generating a reference signal S R of frequency F R ; phase detector means responsive to S N and S R to produce an output signal whose amplitude is representative of the phase therebetween; (Y+Z) sample and hold circuits each responsive, when enabled, to sample and hold the output signal of said phase detector; second means responsive to said divided output signal S N to successively and cyclically enable each of said sample and hold circuits to sample and hold the output signal of said phase detector means during one of said divisions; and third means for summing the contents of said sample and hold circuits each division cycle to produce a control signal of substantially constant amplitude for any given values of N, Y and Z; said VCO responsive to said control signal to supply a substantially constant frequency output signal to said dividing means such that F N =F R .

Claim 8

A fractional frequency synthesizer comprising: a voltage-controlled oscillator (VCO) for generating an output signal S VCO of frequency F VCO ; dividing means for dividing F VCO by division cycles with each division cycle consisting of the division of F VCO by N, Y times, and by (N+1), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , and where Y and Z are integers; first means for generating a reference signal S R of frequency F R ; phase detector means responsive to S N and S R to produce an output signal whose amplitude is representative of the phase therebetween; (Y+Z) sample and hold circuits each responsive, when enabled, to sample and hold the output signal of said phase detector; second means responsive to said divided output signal S N to successively and cyclically enable each of said sample and hold circuits to sample and hold the output signal of said phase detector means during one of said divisions; and third means for summing the contents of said sample and hold circuits each division cycle to produce a control signal of substantially constant amplitude for any given values of N, Y and Z; said VCO responsive to said control signal to supply a substantially constant frequency output signal to said dividing means such that F N =F R .

Claim 9

A fractional frequency synthesizer comprising: a voltage-controlled oscillator (VCO) for producing an output signal S VCO having a variable frequency F VCO ; means for generating first and second control signals; divider means responsive to said first and second control signals to divide said frequency F VCO by division cycles with each division cycle consisting of dividing by N, Y times, and by (N+1), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , and where Y and Z are integers; a reference signal generating means for generating a reference signal S R having a frequency F R ; phase detector means responsive to said output signal S N and said reference signal S R to produce a control signal whose amplitude is representative of the phase therebetween; a plurality of sample and hold circuits each responsive, when enabled, to sample and hold the output signal of said phase detector means; commutator means responsive to said divided output signal S N to successively enable said sample and hold circuits to each sample and hold the output signal of said phase detector during a respective division of each division cycle; summing means for summing the contents of said sample and hold circuits during each division cycle to produce a substantially constant d.c. output signal; and loop filter means for filtering the output signal of said summing means; said VCO responsive to said filtered output of said summing means to supply a substantially constant frequency output signal to said divider means for any given values of N, Y and Z.

Claim 10

A fractional frequency synthesizer comprising: a voltage-controlled oscillator (VCO) for producing an output signal S VCO having a variable frequency F VCO ; means for generating first and second control signals; divider means responsive to said first and second control signals to divide said frequency F VCO by division cycles with each division cycle consisting of dividing by N, Y times, and by (N+1), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , and where Y and Z are integers; a reference signal generating means for generating a reference signal S R having a frequency F R ; phase detector means responsive to said output signal S N and said reference signal S R to produce a control signal whose amplitude is representative of the phase therebetween; a plurality of sample and hold circuits each responsive, when enabled, to sample and hold the output signal of said phase detector means; commutator means responsive to said divided output signal S N to successively enable said sample and hold circuits to each sample and hold the output signal of said phase detector during a respective division of each division cycle; summing means for summing the contents of said sample and hold circuits during each division cycle to produce a substantially constant d.c. output signal; and loop filter means for filtering the output signal of said summing means; said VCO responsive to said filtered output of said summing means to supply a substantially constant frequency output signal to said divider means for any given values of N, Y and Z.

Claim 11

In a fractional frequency synthesizer comprising a voltage-controlled oscillator (VCO) for generating an output signal S VCO of frequency F VCO , dividing means for the division of f VCO by N, Y times, and by (N+M), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , and where Y, M and Z are integers, a reference signal generating means for generating a reference signal S R of frequency F R , and phase detector means responsive to S N and S R to produce an output signal whose amplitude is representative of the phase therebetween; a method of removing perturbations from the output of the VCO comprising the steps of: detecting the output signal of said phase detector means during each division of F VCO in each division cycle; averaging the amplitudes of said detected output signals to produce a d.c. control signal whose amplitude is substantially constant and proportional to the average of the amplitudes of said detected output signals; and supplying said d.c. control signal to said VCO to cause the VCO to produce an output signal of a substantially constant frequency F VCO such that F N =F R .

Claim 12

In a fractional frequency synthesizer comprising a voltage-controlled oscillator (VCO) for generating an output signal S VCO of frequency F VCO , dividing means for the division of f VCO by N, Y times, and by (N+M), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , and where Y, M and Z are integers, a reference signal generating means for generating a reference signal S R of frequency F R , and phase detector means responsive to S N and S R to produce an output signal whose amplitude is representative of the phase therebetween; a method of removing perturbations from the output of the VCO comprising the steps of: detecting the output signal of said phase detector means during each division of F VCO in each division cycle; averaging the amplitudes of said detected output signals to produce a d.c. control signal whose amplitude is substantially constant and proportional to the average of the amplitudes of said detected output signals; and supplying said d.c. control signal to said VCO to cause the VCO to produce an output signal of a substantially constant frequency F VCO such that F N =F R .

Claim 13

In a fractional frequency synthesizer comprising a voltage-controlled oscillator (VCO) for generating an output signal S VCO of frequency F VCO , dividing means for the division of F VCO by N, Y times, and by (N+M), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , and where Y, M and Z are integers, a reference signal generating means for generating a reference signal S R of frequency F R , and phase detector means responsive to S N and S R to produce an output signal whose amplitude is representative of the phase therebetween; a method of removing perturbations from the output of the VCO comprising the steps of: sampling and holding the output signal of said phase detector means during each division of each division cycle; summing and averaging the amplitudes of said samplings to produce a d.c. control signal whose amplitude is constant and proportional to the average of the amplitudes of said samplings; and supplying said d.c. control signal to said VCO to cause the VCO to produce an output signal of a constant frequency F VCO such that F N =F R .

Claim 14

In a fractional frequency synthesizer comprising a voltage-controlled oscillator (VCO) for generating an output signal S VCO of frequency F VCO , dividing means for the division of F VCO by N, Y times, and by (N+M), Z times, in an iterative manner to produce a divided output signal S N of frequency F N , and where Y, M and Z are integers, a reference signal generating means for generating a reference signal S R of frequency F R , and phase detector means responsive to S N and S R to produce an output signal whose amplitude is representative of the phase therebetween; a method of removing perturbations from the output of the VCO comprising the steps of: sampling and holding the output signal of said phase detector means during each division of each division cycle; summing and averaging the amplitudes of said samplings to produce a d.c. control signal whose amplitude is constant and proportional to the average of the amplitudes of said samplings; and supplying said d.c. control signal to said VCO to cause the VCO to produce an output signal of a constant frequency F VCO such that F N =F R .