US4471242A
Expired / Lapsed
US
⏱️ 0.0 years remaining
TTL to CMOS Input buffer
Assignee: Motorola Solutions Inc
•
Filing: 1981-12-21
•
Granted: 1984-09-11
•
Expires: 2001-12-21
Abstract
Abstract A TTL to CMOS input buffer accomplishes buffering a TTL signal to a CMOS signal without requiring current flow through a CMOS input inverter in a static condition by introducing a reference voltage to match the lowest level of a logic "1" of the TTL signal. The input inverter has a P channel transistor which, by having a source at the reference voltage, does not turn on when the TTL signal is at the lowest level of a logic "1". The reference voltage is selected to be less than the lowest level of a logic "1" minus the threshold voltage of the P channel transistor.
Inventors
- 👤 Glenn E. Noufer
- 👤 William J. Donoghue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
303 words
A TTL to CMOS input buffer for providing complementary output signals representative of a first logic state when a TTL input signal is between a TTL supply voltage and a TTL reference voltage, comprising: a first transistor of a first conductivity type having a characteristic threshold voltage and having a control electrode for receiving the TTL signal, a first current electrode for receiving a CMOS reference voltage, and a second current electrode for providing a first output signal; a first transistor of a second conductivity type having a control electrode coupled to the control electrode of the first transistor of the first conductivity type, a first current electrode coupled to a first power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor of the first conductivity type; reference voltage generator means coupled to a second power supply terminal and the first power supply terminal for providing the CMOS reference voltage at a voltage which is no closer to the first power supply voltage than the TTL reference voltage minus the threshold voltage of the first transistor of the first conductivity type; a second transistor of the first conductivity type having a control electrode coupled to the second current electrode of the first transistor of the first conductivity type, a first current electrode coupled to the CMOS reference voltage, and a second current electrode for providing a second output signal which is complementary to the first output signal; and a second transistor of the second conductivity type having a control electrode coupled to the control electrode of the second transistor of the first conductivity type, a first current electrode coupled to the first power supply voltage, and a second current electrode coupled to the second current electrode of the second transistor of the first conductivity type.
Claim 2
Dependent Claim
303 words
A TTL to CMOS input buffer for providing complementary output signals representative of a first logic state when a TTL input signal is between a TTL supply voltage and a TTL reference voltage, comprising: a first transistor of a first conductivity type having a characteristic threshold voltage and having a control electrode for receiving the TTL signal, a first current electrode for receiving a CMOS reference voltage, and a second current electrode for providing a first output signal; a first transistor of a second conductivity type having a control electrode coupled to the control electrode of the first transistor of the first conductivity type, a first current electrode coupled to a first power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor of the first conductivity type; reference voltage generator means coupled to a second power supply terminal and the first power supply terminal for providing the CMOS reference voltage at a voltage which is no closer to the first power supply voltage than the TTL reference voltage minus the threshold voltage of the first transistor of the first conductivity type; a second transistor of the first conductivity type having a control electrode coupled to the second current electrode of the first transistor of the first conductivity type, a first current electrode coupled to the CMOS reference voltage, and a second current electrode for providing a second output signal which is complementary to the first output signal; and a second transistor of the second conductivity type having a control electrode coupled to the control electrode of the second transistor of the first conductivity type, a first current electrode coupled to the first power supply voltage, and a second current electrode coupled to the second current electrode of the second transistor of the first conductivity type.
Claim 3
Dependent Claim
493 words
A TTL to CMOS input buffer for providing an output signal in a first logic state when a TTL input signal is between a TTL supply voltage and a TTL reference voltage, comprising: a first transistor of a first conductivity type having a characteristic threshold voltage and having a control electrode for receiving the TTL signal, a first current electrode for receiving a CMOS reference voltage, and a second current electrode for providing a first output; a first transistor of a second conductivity type having a control electrode coupled to the control electrode of the first transistor of the first conductivity type, a first current electrode coupled to a first power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor of the first conductivity type; reference voltage generator means coupled to a second power supply terminal and the first power supply terminal for providing the CMOS reference voltage at a voltage which is no closer to the first power supply voltage than the TTL reference voltage minus the threshold voltage of the first transistor of the first conductivity type; a second transistor of the first conductivity type having a control electrode coupled to the second current electrode of the first transistor of the first conductivity type, a first current electrode coupled to the CMOS reference voltage, and a second current electrode; a second transistor of the second conductivity type having a control electrode coupled to the control electrode of the second transistor of the first conductivity type, a first current electrode coupled to the first power supply voltage, and a second current electrode coupled to the second current electrode of the second transistor of the first conductivity type; a third transistor of the second conductivity type having a control electrode coupled to the second current electrode of the second transistor of the first conductivity type, a first current electrode coupled to the first power supply terminal, and a second current electrode; a third transistor of the first conductivity type having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the second current electrode of the third transistor of the second conductivity type, and a control electrode; a fourth transistor of the second conductivity type having a control electrode coupled to the second current electrode of the first transistor of the first conductivity type, a first current electrode coupled to the first power supply terminal, and a second current electrode for providing a second output coupled to the control electrode of the third transistor of the first conductivity type; and a fourth transistor of the first conductivity type having a control electrode coupled to the second current electrode of the third transistor of the second conductivity type, a first current electrode coupled to the second power supply terminal, and a second current electrode coupled to the second current electrode of the fourth transistor of the second conductivity type.
Claim 4
Dependent Claim
493 words
A TTL to CMOS input buffer for providing an output signal in a first logic state when a TTL input signal is between a TTL supply voltage and a TTL reference voltage, comprising: a first transistor of a first conductivity type having a characteristic threshold voltage and having a control electrode for receiving the TTL signal, a first current electrode for receiving a CMOS reference voltage, and a second current electrode for providing a first output; a first transistor of a second conductivity type having a control electrode coupled to the control electrode of the first transistor of the first conductivity type, a first current electrode coupled to a first power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor of the first conductivity type; reference voltage generator means coupled to a second power supply terminal and the first power supply terminal for providing the CMOS reference voltage at a voltage which is no closer to the first power supply voltage than the TTL reference voltage minus the threshold voltage of the first transistor of the first conductivity type; a second transistor of the first conductivity type having a control electrode coupled to the second current electrode of the first transistor of the first conductivity type, a first current electrode coupled to the CMOS reference voltage, and a second current electrode; a second transistor of the second conductivity type having a control electrode coupled to the control electrode of the second transistor of the first conductivity type, a first current electrode coupled to the first power supply voltage, and a second current electrode coupled to the second current electrode of the second transistor of the first conductivity type; a third transistor of the second conductivity type having a control electrode coupled to the second current electrode of the second transistor of the first conductivity type, a first current electrode coupled to the first power supply terminal, and a second current electrode; a third transistor of the first conductivity type having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the second current electrode of the third transistor of the second conductivity type, and a control electrode; a fourth transistor of the second conductivity type having a control electrode coupled to the second current electrode of the first transistor of the first conductivity type, a first current electrode coupled to the first power supply terminal, and a second current electrode for providing a second output coupled to the control electrode of the third transistor of the first conductivity type; and a fourth transistor of the first conductivity type having a control electrode coupled to the second current electrode of the third transistor of the second conductivity type, a first current electrode coupled to the second power supply terminal, and a second current electrode coupled to the second current electrode of the fourth transistor of the second conductivity type.
References Cited (Backward Citations)
US3675144A
Cited
US3739194A
Cited
US3937982A
Cited
US3975649A
Cited
US4045691A
Cited
US4039862A
Cited
US4048518A
Cited
US4128775A
Cited
US4342928A
Cited
US4380710A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-11 | 1988-03-12 | 1988-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-11 | 1992-03-12 | 1992-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-11 | 1996-03-12 | 1996-09-11 | $7700.00 | Window Closed / Lapsed |