Data transfer system in which time for transfer of data to a memory is matched to time required to store data in memory

Claim 2

A data transfer system comprising: (a) a first memory having a memory capacity of a plurality of n-bit data and allowing data access bit by bit; (b) a shift register having a storage capacity of n bits and including a first input/output section for inputting and outputting n-bit data in parallel, a pulse input terminal to which pulse signals are applied and a second input/output section connected to said first memory for transferring said n-bit data to or receiving said n-bit data from said first memory bit by bit, each bit being transferred in time with the receipt of one of said pulse signals at said pulse input terminal; (c) a second memory having a memory capacity of at least a plurality of n-bit data for inputting and outputting n-bit data in parallel; (d) clock signal generator means for generating clock signals; (e) transfer means connected to receive said clock signals from said clock signal generator means for transferring n-bit data in parallel between said first input/output section of said shift register and said second memory once during each successive period of N clock signals received, where N is greater than n; and (f) frequency dividing means connected to said clock signal generator means for frequency-dividing said clock signals by a factor of n/N and for supplying the frequency-divided pulse signals to said pulse input terminal of said shift register.

Claim 3

A data transfer system according to claim 1 wherein said transfer means includes a register having a storage capacity of at least one n-bit data and which is connected to said first input/output section of said shift register, a data bus connected between said register and said second memory for transmitting data therebetween and a central processing unit for controlling the transmission of the data transferred through said data bus in response to clock signals received from said clock signal generator means.

Claim 4

A data transfer system comprising: (a) clock signal generator means for generating clock signals; (b) a first memory having a memory capacity of a plurality of n-bit data and including means for writing data bit by bit into said first memory at a rate of n bits during each period of N clock signals generated by said clock signal generator means; (c) a shift register having a storage capacity of n bits and including input means for inputting n-bit data into said shift register in parallel, a pulse input terminal to which pulse signals are applied and output means connected to said first memory for transferring said n-bit data to said first memory bit by bit, each bit being transferred in time with receipt of one of said pulse signals at said pulse input terminal; (d) a second memory having a memory capacity of at least a plurality of n-bit data and including means for outputting n-bit data in parallel; (e) transfer means connected to said second memory, said shift register and said clock signal generating means for transferring n-bit data in parallel from said second memory to said shift register once during each successive period of N clock signals received from said clock signal generator means, where N is greater than n, including data processor means programmed to effect said data transfer within said period of N clock signals; and (f) frequency dividing means connected to said clock signal generator means for frequency-dividing said clock signals by a factor of n/N and for supplying the frequency-divided pulse signals to said pulse input terminal of said shift register.

Claim 5

A data transfer system comprising: (a) clock signal generator means for generating clock signals; (b) a first memory having a memory capacity of a plurality of n-bit data and including means for writing data bit by bit into said first memory at a rate of n bits during each period of N clock signals generated by said clock signal generator means; (c) a shift register having a storage capacity of n bits and including input means for inputting n-bit data into said shift register in parallel, a pulse input terminal to which pulse signals are applied and output means connected to said first memory for transferring said n-bit data to said first memory bit by bit, each bit being transferred in time with receipt of one of said pulse signals at said pulse input terminal; (d) a second memory having a memory capacity of at least a plurality of n-bit data and including means for outputting n-bit data in parallel; (e) transfer means connected to said second memory, said shift register and said clock signal generating means for transferring n-bit data in parallel from said second memory to said shift register once during each successive period of N clock signals received from said clock signal generator means, where N is greater than n, including data processor means programmed to effect said data transfer within said period of N clock signals; and (f) frequency dividing means connected to said clock signal generator means for frequency-dividing said clock signals by a factor of n/N and for supplying the frequency-divided pulse signals to said pulse input terminal of said shift register.

Claim 6

A data transfer system according to claim 3, wherein said transfer means includes register means having a storage capacity of at least one n-bit data and which is connected to said shift register for storing n-bit data received from said second memory and for transferring said n-bit data to said shift register, a data bus connected between said register means and said second memory for transmitting data therebetween and a central processing unit for controlling said data bus in response to clock signals received from said clock signal generator means.

Claim 7

A data transfer system comprising: (a) clock signal generator means for generating clock signals; (b) a first memory having a memory capacity of a plurality of n-bit data and including means for outputting data bit by bit from said first memory at a rate of n bits during each period of N clock signals generated by said clock signal generator means; (c) a shift register having a storage capacity of n bits and including output means for outputting n-bit data from said shift register in parallel, a pulse input terminal to which pulse signals are applied and input means connected to said first memory for storing said n-bit data from said first memory into said shift register bit by bit, each bit being stored in time with receipt of one of said pulse signals at said pulse input terminal; (d) a second memory having a memory capacity of at least a plurality of n-bit data and including means for inputting n-bit data in parallel; (e) transfer means connected to said second memory, said shift register and said clock signal generator means for transferring n-bit data in parallel from said shift register to said second memory once during each successive period of N clock signals received from said clock signal generator means, where N is greater than n, including data processor means programmed to effect said data transfer within said period of N clock signals; and (f) frequency dividing means connected to said clock signal generator means for frequency-dividing said clock signals by a factor of n/N and for supplying the frequency-divided pulse signals to said pulse input terminal of said shift register.

Claim 8

A data transfer system comprising: (a) clock signal generator means for generating clock signals; (b) a first memory having a memory capacity of a plurality of n-bit data and including means for outputting data bit by bit from said first memory at a rate of n bits during each period of N clock signals generated by said clock signal generator means; (c) a shift register having a storage capacity of n bits and including output means for outputting n-bit data from said shift register in parallel, a pulse input terminal to which pulse signals are applied and input means connected to said first memory for storing said n-bit data from said first memory into said shift register bit by bit, each bit being stored in time with receipt of one of said pulse signals at said pulse input terminal; (d) a second memory having a memory capacity of at least a plurality of n-bit data and including means for inputting n-bit data in parallel; (e) transfer means connected to said second memory, said shift register and said clock signal generator means for transferring n-bit data in parallel from said shift register to said second memory once during each successive period of N clock signals received from said clock signal generator means, where N is greater than n, including data processor means programmed to effect said data transfer within said period of N clock signals; and (f) frequency dividing means connected to said clock signal generator means for frequency-dividing said clock signals by a factor of n/N and for supplying the frequency-divided pulse signals to said pulse input terminal of said shift register.

Claim 9

A data transfer system according to claim 5, wherein said transfer means includes register means having a storage capacity of at least one n-bit data and which is connected to said shift register for storing n-bit data received from said shift register and for transferring said n-bit data to said second memory, a data bus connected between said register means and said second memory for transmitting data therebetween and a central processing unit for controlling said data bus in response to clock signals received from said clock signal generator means.