Electrically erasable programmable read only memory

Claim 1

An electrically erasable and programmable read only memory device comprising: a semiconductive substrate of one conductivity type; a plurality of memory cells arranged on said substrate in a matrix form, each memory cell comprising; first and second diffusion layers which are formed on said substrate to have a conductivity type opposite to that of said substrate, and which define a channel region therebetween, and a floating gate insulated from said substrate; first control electrode layers capacitively and commonly coupled to floating gates of a first group of said plurality of memory cells which are included in each array of a first number of cell arrays aligned in a first direction of said memory cell matrix, said first control electrode layers being insulated from said substrate; second control electrode layers capacitively and commonly coupled to floating gates of a second group of said plurality of memory cells which are included in each array of a second number of cell arrays aligned in a second direction that intersects said first direction of said memory cell matrix substantially at right angles, said second control electrode layers being insulated from said substrate and said first control electrode layers; third electrode layers each of which is commonly coupled to the first diffusion layers of said memory cells included in the corresponding one of said first number of cell arrays and which are electrically separated from said substrate and insulated from said floating gates and said first and second electrode layers, said third electrode layers being capactivively and commonly coupled to said floating gates of said memory cells included in each of said first number of cell arrays; and means, electrically connected to said first, second and third electrode layers, for controlling the level of a voltage applied to said first, second and third electrode layers so as to selectively charge or discharge carriers only in or from the floating gate of an arbitrary memory cell of said matrix memory cells.