§
PatentCue
Patent Intelligence
Join Waitlist Sign In
← Back to Patent Explorer
US4488162A Expired / Lapsed US ⏱️ 0.0 years remaining

Self-aligned metal field effect transistor integrated circuits using polycrystalline silicon gate electrodes

Assignee: International Business Machines Corp
•
Filing: 1983-01-03
•
Granted: 1984-12-11
•
Expires: 2003-01-03
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A self-aligned metal process and resulting structure is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. All gate electrodes are composed of polycrystalline silicon while the remaining contacts are composed of metal. The insulation between the metal contacts and the polycrystalline silicon is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal/polycrystalline silicon and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A first layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are in those areas designated to be the gate regions of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is formed hereat. A second polycrystalline silicon gate electrode is formed over the gate dielectric and between certain of said narrow dimensioned regions. The remaining first polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions. A blanket layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached. The plastic material is then removed leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less. The source and drain electrodes are thusly formed.

Inventors

  • 👤 Chakrapani G. Jambotkar

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 00:04
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D62/00; H10D62/01; H10D62/021; H10D64/00; H10D64/01; H10D64/011

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 142 words
A substantially planar self-aligned field effect transistor integrated circuit structure comprising: a silicon body a pattern of narrow dimensioned dielectric regions on a major surface of said body; a gate dielectric layer on the said surface of said body forming a portion of said field effect transistor structure, and between certain of said narrow dimensioned regions; PN junction regions within said body forming a portion of said field effect transistor structure and in close proximity to and associated with the channel under said gate dielectric layer; doped polycrystalline silicon gate electrodes on the surface of said gate dielectric layer between certain of said narrow dimensioned regions; and metal electrical contacts to said PN regions filling spaces between the remaining said narrow dimensioned regions and which contacts are self-aligned to said narrow regions and substantially planar with the tops of said narrow regions.
Claim 2
Dependent Claim 142 words
A substantially planar self-aligned field effect transistor integrated circuit structure comprising: a silicon body a pattern of narrow dimensioned dielectric regions on a major surface of said body; a gate dielectric layer on the said surface of said body forming a portion of said field effect transistor structure, and between certain of said narrow dimensioned regions; PN junction regions within said body forming a portion of said field effect transistor structure and in close proximity to and associated with the channel under said gate dielectric layer; doped polycrystalline silicon gate electrodes on the surface of said gate dielectric layer between certain of said narrow dimensioned regions; and metal electrical contacts to said PN regions filling spaces between the remaining said narrow dimensioned regions and which contacts are self-aligned to said narrow regions and substantially planar with the tops of said narrow regions.
Claim 3
Dependent Claim 20 words
The integrated circuit structure of claim 1 wherein silicon dioxide regions within said body isolate said transistors from one another.
Claim 4
Dependent Claim 15 words
The integrated circuit structure of claim 1 wherein said PN junctions are sources and drains.
Claim 5
Dependent Claim 37 words
The integrated circuit structure of claim 3 wherein said sources/drains are in said silicon body below the said certain of said narrow dimensioned regions and said metal electrical contacts are made to the edge of said sources/drains.
Claim 6
Dependent Claim 24 words
The integrated circuit structure of claim 1 wherein the said metal electrical contacts are composed of aluminum and said polycrystalline silicon is N type.
Claim 7
Dependent Claim 44 words
The integrated circuit structure of claim 5 wherein said PN junction comprise an N region in a P- silicon body in which two such N regions are closely adjacent and are respectively connected as source and drain for said field effect transistor integrated circuit.
Claim 8
Dependent Claim 21 words
The integrated circuit structure of claim 6 wherein a P channel region is located between said source and drain N regions.
Claim 9
Dependent Claim 24 words
The integrated circuit structure of claim 1 wherein said polycrystalline silicon gate electrode is electrically contacted on its edge by a metal electrical contact.
Claim 10
Dependent Claim 25 words
The integrated circuit structure of claim 1 wherein said polycrystalline silicon gate electrode is electrically contacted by a higher level metal electrical contact from above.
Claim 11
Dependent Claim 146 words
A substantially planar self-aligned field effect transistor integrated circuit structure comprising: a silicon body; a pattern of narrow dimensioned dielectric regions on a major surface of said body; a gate dielectric layer on said major surface of said body forming a portion of said field effect transistor integrated circuit between certain of said narrow dimensioned regions; PN junction source/drain regions located directly under certain portions of said narrow dimensioned regions and associated with a channel under said gate dielectric layer; doped polycrystalline silicon gate electrodes on the surface of said gate dielectric layer between said certain of said narrow dimensioned regions; and metal electrical contacts made to the edges of said PN junction regions while filling the spaces between the remaining said narrow dimensioned regions and which contacts are self-aligned to said narrow dimensioned regions and substantially planar with the tops of said narrow dimensioned regions.
Claim 12
Dependent Claim 146 words
A substantially planar self-aligned field effect transistor integrated circuit structure comprising: a silicon body; a pattern of narrow dimensioned dielectric regions on a major surface of said body; a gate dielectric layer on said major surface of said body forming a portion of said field effect transistor integrated circuit between certain of said narrow dimensioned regions; PN junction source/drain regions located directly under certain portions of said narrow dimensioned regions and associated with a channel under said gate dielectric layer; doped polycrystalline silicon gate electrodes on the surface of said gate dielectric layer between said certain of said narrow dimensioned regions; and metal electrical contacts made to the edges of said PN junction regions while filling the spaces between the remaining said narrow dimensioned regions and which contacts are self-aligned to said narrow dimensioned regions and substantially planar with the tops of said narrow dimensioned regions.
Claim 13
Dependent Claim 24 words
The integrated circuit structure of claim 10 wherein the said metal electrical contacts are composed of aluminum and said polycrystalline silicon is N type.
Claim 14
Dependent Claim 44 words
The integrated circuit structure of claim 11 wherein said PN junction comprise an N region in a P- silicon body in which two such N regions are closely adjacent and are respectively connected as source and drain for said field effect transistor integrated circuit.
Claim 15
Dependent Claim 21 words
The integrated circuit structure of claim 12 wherein a P channel region is located between said source and drain N regions.

References Cited (Backward Citations)

US4209350A Cited
US4209349A Cited
US4249968A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-12-11 1988-06-11 1988-12-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-12-11 1992-06-11 1992-12-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-12-11 1996-06-11 1996-12-11 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag