Memory cell with thick oxide at least as deep as channel stop

Claim 2

A semiconductor device having at least one memory cell comprising a semiconductor body having a surface region of a first conductivity type which is covered with a thick insulating layer, at least one aperture in the thick insulating layer at the area of a storage element of the memory cell, said storage element comprising a capacitor having a first plate of electrically conductive material and a part of the semiconductor body which is separated from the first plate by a dielectric, which forms a second plate of the capacitor and which is connected to a semiconductor zone of a second conductivity type opposite to the first via a channel region controllable by a gate electrode, the thick insulating layer being thicker than the dielectric and the gate electrode being connected to a first selection line of conductive material of the memory cell, said selection line extending above said semiconductor zone, which zone forms part of a second selection line of the memory cell, said semiconductor zone being present substantially entirely below the thick insulating layer, which thick insulating layer at the area of the semiconductor zone extends into the semiconductor body down to a depth different from the depth at other places at the surface of said body, and at least one channel stopping region of said first conductivity type located beneath said thick insulating layer and adjacent to but spaced apart from said semiconductor zone, so that no p-n junction is formed between said channel stopping region and said semiconductor zone, said at least one channel stopping region comprising substantially uniform channel stopping regions present between several memory cells below the thick insulating layer, the thick insulating layer at the area of the semiconductor zone extending into the semiconductor body down to a depth which is at least equal to the maximum depth of the channel stopping regions.

Claim 3

A semiconductor device having at least one memory cell comprising a semiconductor body having a surface region of a first conductivity type which is covered with a thick insulating layer, at least one aperture in the thick insulating layer at the area of a storage element of the memory cell, said storage element comprising a capacitor having a first plate of electrically conductive material and a part of the semiconductor body which is separated from the first plate by a dielectric, which forms a second plate of the capacitor and which is connected to a semiconductor zone of a second conductivity type opposite to the first via a channel region controllable by a gate electrode, the thick insulating layer being thicker than the dielectric and the gate electrode being connected to a first selection line of conductive material of the memory cell, said selection line extending above said semiconductor zone, which zone forms part of a second selection line of the memory cell, said semiconductor zone being present substantially entirely below the thick insulating layer, which thick insulating layer at the area of the semiconductor zone extends into the semiconductor body down to a depth different from the depth at other places at the surface of said body, and at least one channel stopping region of said first conductivity type located beneath said thick insulating layer and adjacent to but spaced apart from said semiconductor zone, so that no p-n junction is formed between said channel stopping region and said semiconductor zone, the thick insulating layer at the area of the semiconductor zone having a larger thickness than that of the remaining portions of the thick insulating layer, and said at least one channel stopping region comprising substantially uniform channel stopping regions present between several memory cells below the thick insulating layer, the thick insulating layer at the area of the semiconductor zone extending into the semiconductor body down to a depth which is at least equal to the maximum depth of the channel stopping regions.

Claim 4

A semiconductor device having at least one memory cell comprising a semiconductor body having a surface region of a first conductivity type which is covered with a thick insulating layer, at least one aperture in the thick insulating layer at the area of a storage element of the memory cell, said storage element comprising a capacitor having a first plate of electrically conductive material and a part of the semiconductor body which is separated from the first plate by a dielectric, which forms a second plate of the capacitor and which is connected to a semiconductor zone of a second conductivity type opposite to the first via a channel region controllable by a gate electrode, the thick insulating layer being thicker than the dielectric and the gate electrode being connected to a first selection line of conductive material of the memory cell, said selection line extending above said semiconductor zone, which zone forms part of a second selection line of the memory cell, said semiconductor zone being present substantially entirely below the thick insulating layer, which thick insulating layer at the area of the semiconductor zone extends into the semiconductor body down to a depth different from the depth at other places at the surface of said body, and at least one channel stopping region of said first conductivity type located beneath said thick insulating layer and adjacent to but spaced apart from said semiconductor zone, so that no p-n junction is formed between said channel stopping region and said semiconductor zone, the thick insulating layer at the area of the semiconductor zone having a larger thickness than that of the remaining portions of the thick insulating layer, and said at least one channel stopping region comprising substantially uniform channel stopping regions present between several memory cells below the thick insulating layer, the thick insulating layer at the area of the semiconductor zone extending into the semiconductor body down to a depth which is at least equal to the maximum depth of the channel stopping regions.

Claim 5

A semiconductor device as claimed in claim 1 or 2, characterized in that the maximum lateral distance between the semiconductor zone and the channel stopping region is at most about 0.5 micrometer.

Claim 6

A semiconductor device as claimed in claim 1 or 2, characterized in that the semiconductor zone forms part of a common buried selection line for several memory cells.

Claim 7

A semiconductor device as claimed in claim 1 or 2, characterized in that the first plate of conductive material of the capacitor comprises polycrystalline silicon.

Claim 8

A semiconductor device as claimed in claim 1 or 2, characterized in that the first selection line belongs to a first group of lines which, together with a second group of lines comprising the second selection line, forms a system of cross-bars with the memory cells being present at the area of crossings of the cross-bar system.