Write protected memory

Claim 1

A central processor unit (CPU) including a memory and a microprocessor, said CPU being operative in a write enable mode for writing information into said memory, and further being operative in a write protect mode to cause said microprocessor to branch to a correction microprogram in response to a write memory command generated by said microprocessor, said CPU comprising: microprocessor means for generating a plurality of address signals on an address bus, generating a plurality of data signals on a data bus and generating a plurality of bus cycle signals; write protect means responsive to the plurality of address signals in a first state, a first of the plurality of data signals in a first state, and a first bus cycle signal for generating a first signal in a first state indicative of said write protect mode, said write protect means being responsive to the plurality of address signals in the first state, the first of the plurality of data signals in a second state, and the first bus cycle signal for generating the first signal in a second state, said write protect means being further responsive to the first signal in the first state and a second bus cycle signal for generating a second signal indicative of said memory write mode; memory means responsive to the second bus cycle signal, the second signal for writing a data word representative of the plurality of data signals received from said data bus at an address location of said memory specified by the plurality of address signals in a second state; and nonmaskable interrupt means responsive to the first signal and the second bus cycle signal for generating a third signal for causing said microprocessor means to interrupt a current microprogram to branch to the correction microprogram, wherein said microprocessor means includes, said microprocessor for generating a plurality of command signals to identify the type of bus cycle that said CPU is starting to execute; a multiplexer responsive to the plurality of command signals in a first state for generating the second bus cycle signal; and a bus controller responsive to the plurality of command signals in a second state for generating the first bus cycle signal.