US4489402A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1982-04-22
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Granted: 1984-12-18
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Expires: 2002-04-22
Abstract
Abstract A semiconductor memory device provides redundancy using a decoder which examines a memory address and outputs the contents of memory at that address if the decoder determines that the address signal is selecting a correct bit cell in the memory, or clamps the output at a predetermined level if the decoder determines that the address signal is selecting an error bit cell in the memory.
Inventors
- 👤 Shinji Saitoh
- 👤 Junichi Miyamoto
- 👤 Kazuaki Ichinose
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:08
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
173 words
A semiconductor memory device comprising: a memory for storing data; a first decoder circuit for receiving an address signal to decode and designate an address of said memory; a sense circuit for sensing data stored in said memory at said designated address; a second decoder circuit for receiving said address signal and for producing a logic output signal at a first logic level if said address signal is for selecting a correct bit cell in said memory and for producing an output signal at a second logic level if said address signal is for selecting an error bit cell in said memory; and logic circuit means for receiving the data sensed by said sense circuit and the logic output signal from said second decoder circuit, and for transmitting the sensed data from said sense circuit without change when the logic output signal from said second decoder circuit is at said first level, and for clamping said sensed data at a predetermined level when said logic output signal is at said second logic level.
Claim 2
Dependent Claim
173 words
A semiconductor memory device comprising: a memory for storing data; a first decoder circuit for receiving an address signal to decode and designate an address of said memory; a sense circuit for sensing data stored in said memory at said designated address; a second decoder circuit for receiving said address signal and for producing a logic output signal at a first logic level if said address signal is for selecting a correct bit cell in said memory and for producing an output signal at a second logic level if said address signal is for selecting an error bit cell in said memory; and logic circuit means for receiving the data sensed by said sense circuit and the logic output signal from said second decoder circuit, and for transmitting the sensed data from said sense circuit without change when the logic output signal from said second decoder circuit is at said first level, and for clamping said sensed data at a predetermined level when said logic output signal is at said second logic level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-18 | 1988-06-18 | 1988-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-18 | 1992-06-18 | 1992-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-18 | 1996-06-18 | 1996-12-18 | $7700.00 | Window Closed / Lapsed |