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US4498106A Expired / Lapsed US ⏱️ 0.0 years remaining

Pulse generator for solid-state television camera

Assignee: Hitachi Ltd
•
Filing: 1982-07-28
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Granted: 1985-02-05
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Expires: 2002-07-28
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Abstract

Abstract A pulse generator circuit for a solid-state television camera comprising a first circuit arrangement including a shift register of endless type for obtaining pulses of a horizontal scanning frequency for television, a second circuit arrangement for obtaining necessary pulse trains of the horizontal scanning frequency for a television camera from a plurality of output pulses of the shift register and a third circuit arrangement for dividing the pulse obtained by the second circuit arrangement by two-different factors of mode, n and n+1, and delaying the 1/n frequency-divided mode pulse by 1/2 horizontal scanning period in response to the output pulse from the second circuit arrangement thereby obtaining a frame pulse capable of interlaced scanning.

Inventors

  • 👤 Kazuhiro Sato
  • 👤 Morishi Izumita
  • 👤 Kenji Takahashi
  • 👤 Toshiyuki Akiyama
  • 👤 Shigeki Nishizawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 11:46
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/40; H04; H04N; H04N25/00; H04N5/00; H04N5/04; H04N5/06

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 230 words
A pulse generator circuit for a solid-state television camera comprising: first means for producing pulses of a horizontal scanning frequency, said first means including an oscillator for generating clock pulses, a shift register driven by said clock pulses, said shift register having a number of stages sufficient for dividing a frequency of the clock pulses into the horizontal scanning frequency, said shift register having an output terminal thereof connected with an input terminal thereof so as to form a ring counter circuit, and a pulse generator for generating a pulse to be applied to said input terminal of said shift register for transfer through said shift register; second means for producing pulse trains of the horizontal scanning frequency for the television camera, said pulse trains being produced in response to a plurality of pulses extracted from the stages of said shift register having frequencies which are the same as the horizontal scanning frequency and phases which are different from each other; third means for producing pulses for interlace scanning, said third means including a divider circuit for dividing the pulse train of the horizontal scanning frequency obtained from said second means so that said pulse train is alternately divided by two different factors n and n+1 (n being a positive integer), and delay means for delaying said pulse divided by n for one half of the horizontal scanning time period.
Claim 2
Dependent Claim 230 words
A pulse generator circuit for a solid-state television camera comprising: first means for producing pulses of a horizontal scanning frequency, said first means including an oscillator for generating clock pulses, a shift register driven by said clock pulses, said shift register having a number of stages sufficient for dividing a frequency of the clock pulses into the horizontal scanning frequency, said shift register having an output terminal thereof connected with an input terminal thereof so as to form a ring counter circuit, and a pulse generator for generating a pulse to be applied to said input terminal of said shift register for transfer through said shift register; second means for producing pulse trains of the horizontal scanning frequency for the television camera, said pulse trains being produced in response to a plurality of pulses extracted from the stages of said shift register having frequencies which are the same as the horizontal scanning frequency and phases which are different from each other; third means for producing pulses for interlace scanning, said third means including a divider circuit for dividing the pulse train of the horizontal scanning frequency obtained from said second means so that said pulse train is alternately divided by two different factors n and n+1 (n being a positive integer), and delay means for delaying said pulse divided by n for one half of the horizontal scanning time period.
Claim 3
Dependent Claim 44 words
A pulse generator circuit according to claim 1, wherein said first means further includes a circuit for stopping said shift register from transferring a pulse when a plurality of pulses (including a single pulse continuous over several stages) are present within said shift register.
Claim 4
Dependent Claim 37 words
A pulse generator circuit according to claim 1, wherein said pulse generator starts oscillation when the transferred pulse in said shift register is erased so as to generate a pulse to be transferred in said shift register.
Claim 5
Dependent Claim 45 words
A pulse generator circuit according to claim 1, wherein said delay means further includes a shift register for shifting the pulse divided by n, and a delay circuit delaying the clock pulse driving said shift register for one half of the horizontal scanning time period.
Claim 6
Dependent Claim 37 words
A pulse generator circuit according to claim 2, wherein said pulse generator starts oscillation when the transferred pulse in said shift register is erased so as to generate a pulse to be transferred in said shift register.

References Cited (Backward Citations)

US3422223A Cited
US4080622A Cited
US4079423A Cited
US4278999A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-02-05 1988-08-06 1989-02-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-02-05 1992-08-06 1993-02-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-02-05 1996-08-06 1997-02-05 $7700.00 Window Closed / Lapsed

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