US4502202A
Expired / Lapsed
US
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Method for fabricating overlaid device in stacked CMOS
Assignee: Texas Instruments Inc
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Filing: 1983-06-17
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Granted: 1985-03-05
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Expires: 2003-06-17
Abstract
Abstract In stacked CMOS, a single gate in first level polysilicon is used to address both an n-channel device in the substrate and an overlaid p-channel device. The p-channel polysilicon device has its channel self-aligned to the gate, by the use of a boron-doped oxide at the sidewalls of the gate. This boron-doped oxide provides a dopant source which dopes the second polysilicon layer to provide heavily doped source/drain extension regions which are self-aligned to the gate in first poly. A mask level is still required to pattern the sources and drains, but the self-aligned source/drain extension regions mean that the source/drain mask level can have a reasonable alignment tolerance.
Inventors
- 👤 Satwinder Malhi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:02
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
155 words
A method for fabricating a stacked CMOS device, comprising the steps of; providing a substrate; growing a gate oxide on said substrate; forming a gate electrode in desired gate locations, said gate electrode being formed to have substantially vertically sidewalls in desired gate locations; depositing and anistropically etching a dopant source material, to provide sidewall filaments of said dopant source adjacent to said sidewalls of said gate electrode; depositing a thin polysilicon layer over all, said thin polysilicon layer being insulated from said gate electrode and comprising a second-type dopant; providing a mask over said gate electrode, said mask being wider than the width of said gate electrode, and implanting a heavy concentration of a second-conductivity type dopant into said thin polysilicon layer; whereby said gate electrode addresses both a field effect transistor having first-type sources and drains in said substrate, and a field effect transistor having second-type sources and drains and a polysilicon channel.
Claim 2
Independent Claim
155 words
A method for fabricating a stacked CMOS device, comprising the steps of; providing a substrate; growing a gate oxide on said substrate; forming a gate electrode in desired gate locations, said gate electrode being formed to have substantially vertically sidewalls in desired gate locations; depositing and anistropically etching a dopant source material, to provide sidewall filaments of said dopant source adjacent to said sidewalls of said gate electrode; depositing a thin polysilicon layer over all, said thin polysilicon layer being insulated from said gate electrode and comprising a second-type dopant; providing a mask over said gate electrode, said mask being wider than the width of said gate electrode, and implanting a heavy concentration of a second-conductivity type dopant into said thin polysilicon layer; whereby said gate electrode addresses both a field effect transistor having first-type sources and drains in said substrate, and a field effect transistor having second-type sources and drains and a polysilicon channel.
Claim 3
Dependent Claim
32 words
The method of claim 1, further comprising the subsequent step of: introducing a passivating species into said thin polysilicon layer, to improve the effective mobility of carriers in said thin polysilicon layer.
Claim 4
Dependent Claim
15 words
The method of claim 2, wherein said passivation step comprises exposure to a hydrogen plasma.
Claim 5
Dependent Claim
21 words
The method of claim 10, further comprising the step of: patterning said thin polysilicon layer to achieve a desired device configuration.
Claim 6
Dependent Claim
28 words
The method of claim 1, further comprising the subsequent step of: interconnecting predetermined ones of said first-conductivity-type and said second conductivity-type transistors to achieve a desired circuit function.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-04 | 1988-09-03 | 1989-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-04 | 1992-09-03 | 1993-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-04 | 1996-09-03 | 1997-03-05 | $7700.00 | Window Closed / Lapsed |