Method of manufacturing semiconductor device, including a step of patterning a conductor layer

Claim 1

A method of manufacturing a semiconductor device, including a step of forming a patterned conductor layer, comprising steps of: forming a conductor layer on an insulating layer which is formed on a semiconductor substrate and which has thick and thin portions with a step therebetween; coating a material having an etching rate substantially equal to that of the material of said conductor layer, thereby forming a film so that those portions of a laminated structure consisting of said conductor layer and said film which are on the thin portion of said insulating layer and said step have the same thickness; forming a mask layer of a predetermined pattern on said film; and selectively etching said laminated structure by using said mask layer to cause the surface of the thin portion of said insulating layer to be partially exposed.

Claim 2

A method of manufacturing a semiconductor device, including a step of forming a patterned conductor layer, comprising steps of: forming a conductor layer on an insulating layer which is formed on a semiconductor substrate and which has thick and thin portions with a step therebetween; coating a material having an etching rate substantially equal to that of the material of said conductor layer, thereby forming a film so that those portions of a laminated structure consisting of said conductor layer and said film which are on the thin portion of said insulating layer and said step have the same thickness; forming a mask layer of a predetermined pattern on said film; and selectively etching said laminated structure by using said mask layer to cause the surface of the thin portion of said insulating layer to be partially exposed.

Claim 3

A method of manufacturing a MOS transistor including a step of forming a patterned conductor layer, comprising steps of: forming a pair of impurity regions set apart at a predetermined distance in a surface region of a semiconductor substrate having a conductivity type opposite to said impurity regions; forming a thick insulating film on a surface portion of said semiconductor substrate other than a surface portion thereof which lies between said impurity regions; forming a thin insulating film on the surface portion of said semiconductor substrate which lies between said impurity regions, said thin insulating film forming a step with said thick insulating film; forming contact holes in said thick insulating film, thus exposing said impurity regions, respectively; forming a conductor layer on said thick insulating film and thin insulating film, thereby filling up said contact holes; coating a material having an etching rate substantially equal to that of the material of said conductor layer on said conductor layer, thereby forming a film which has a flat upper surface so that those portions of a laminated structure consisting of said conductor layer and said film which are on said thin insulating film and said step have the same thickness; forming a mask layer of a predetermined pattern on said film; and selectively etching said laminated structure by using said mask layer to cause the surface of said thin insulating film to be partially exposed, thereby forming a gate electrode on said thin insulating film.

Claim 4

A method of manufacturing a MOS transistor including a step of forming a patterned conductor layer, comprising steps of: forming a pair of impurity regions set apart at a predetermined distance in a surface region of a semiconductor substrate having a conductivity type opposite to said impurity regions; forming a thick insulating film on a surface portion of said semiconductor substrate other than a surface portion thereof which lies between said impurity regions; forming a thin insulating film on the surface portion of said semiconductor substrate which lies between said impurity regions, said thin insulating film forming a step with said thick insulating film; forming contact holes in said thick insulating film, thus exposing said impurity regions, respectively; forming a conductor layer on said thick insulating film and thin insulating film, thereby filling up said contact holes; coating a material having an etching rate substantially equal to that of the material of said conductor layer on said conductor layer, thereby forming a film which has a flat upper surface so that those portions of a laminated structure consisting of said conductor layer and said film which are on said thin insulating film and said step have the same thickness; forming a mask layer of a predetermined pattern on said film; and selectively etching said laminated structure by using said mask layer to cause the surface of said thin insulating film to be partially exposed, thereby forming a gate electrode on said thin insulating film.

Claim 5

A method of manufacturing a semiconductor device, including a step of forming a patterned conductor layer, comprising steps of: forming a conductor layer on an insulating film which is formed on a semiconductor substrate and which has a thick portion and a thin portion, said conductor layer being formed such that the upper surface portion thereof on the thin insulating film portion is made substantially equal to or greater than the upper surface portion of said conductor layer on the thick insulating film portion so as to make uniform the substantial thickness of said conductor layer which is defined on the thin insulating film portion; forming a film having a flat upper surface on said conductor layer; removing said film and an upper surface region of said conductor layer so that said conductor layer has an exposed flat upper surface lying above said thick portion; forming a mask layer of a predetermined pattern on said conductor layer; and selectively etching said conductor layer by using said mask layer to cause the surface of the thin portion of said insulating film to be partially exposed.

Claim 6

A method of manufacturing a semiconductor device, including a step of forming a patterned conductor layer, comprising steps of: forming a conductor layer on an insulating film which is formed on a semiconductor substrate and which has a thick portion and a thin portion, said conductor layer being formed such that the upper surface portion thereof on the thin insulating film portion is made substantially equal to or greater than the upper surface portion of said conductor layer on the thick insulating film portion so as to make uniform the substantial thickness of said conductor layer which is defined on the thin insulating film portion; forming a film having a flat upper surface on said conductor layer; removing said film and an upper surface region of said conductor layer so that said conductor layer has an exposed flat upper surface lying above said thick portion; forming a mask layer of a predetermined pattern on said conductor layer; and selectively etching said conductor layer by using said mask layer to cause the surface of the thin portion of said insulating film to be partially exposed.

Claim 7

A method of manufacturing a MOS transistor including a step of forming a patterned layer, comprising steps of: forming a pair of impurity regions set apart at a predetermined distance in a surface region of a semiconductor substrate having a conductivity type opposite to said impurity regions; forming a thick insulating film on a surface portion of said semiconductor substrate other than a surface portion which lies between said impurity regions; forming a thin insulating film on the surface portion of said semiconductor substrate which lies between said impurity regions, said thin insulating film forming a step with said thick insulating film; forming contact holes in said thick insulating film, thus exposing said impurity regions, respectively; forming a conductor layer on said thick insulating film and thin insulating film, thereby filling up said contact holes, said conductor layer being so thick that a laminated structure consisting of said thin insulating film and that portion of said conductor layer which is on said thin insulating film has a substantially uniform thickness; forming a film having a flat upper surface on said conductor layer; removing said film and an upper surface region of said conductor layer so that said conductor layer has an exposed flat upper surface lying above said thick insulating film; forming a mask layer of a predetermined pattern on said conductor layer; and selectively etching said conductor layer by using said mask layer to cause the surface of said thin insulating film to be partially exposed, thereby forming a gate electrode on said thin insulating film.

Claim 8

A method of manufacturing a MOS transistor including a step of forming a patterned layer, comprising steps of: forming a pair of impurity regions set apart at a predetermined distance in a surface region of a semiconductor substrate having a conductivity type opposite to said impurity regions; forming a thick insulating film on a surface portion of said semiconductor substrate other than a surface portion which lies between said impurity regions; forming a thin insulating film on the surface portion of said semiconductor substrate which lies between said impurity regions, said thin insulating film forming a step with said thick insulating film; forming contact holes in said thick insulating film, thus exposing said impurity regions, respectively; forming a conductor layer on said thick insulating film and thin insulating film, thereby filling up said contact holes, said conductor layer being so thick that a laminated structure consisting of said thin insulating film and that portion of said conductor layer which is on said thin insulating film has a substantially uniform thickness; forming a film having a flat upper surface on said conductor layer; removing said film and an upper surface region of said conductor layer so that said conductor layer has an exposed flat upper surface lying above said thick insulating film; forming a mask layer of a predetermined pattern on said conductor layer; and selectively etching said conductor layer by using said mask layer to cause the surface of said thin insulating film to be partially exposed, thereby forming a gate electrode on said thin insulating film.

Claim 13

A method according to any one of claims 1 to 4, wherein said selective etching is anisotropic etching selected from the group consisting of ion etching, sputter etching and reactive ion etching, in which an etching rate in a lateral direction is low.

Claim 16

A method according to any one of claims 1 to 4, wherein said mask layer is a silicon nitride film formed by plasma chemical vapor deposition.

Claim 17

A method according to any one of claims 1 to 4, further comprising a step of ion-implanting an impurity into the surface region of said semiconductor substrate using said conductor layer as a mask after said conductor layer is selectively etched.

Claim 18

A method according to any one of claims 1 to 4, further comprising a step of converting the exposed portions of said semiconductor substrate with a protective film after said conductor layer is selectively etched.