US4513209A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Level detector
Assignee: Panasonic Holdings Corp
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Filing: 1982-02-11
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Granted: 1985-04-23
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Expires: 2002-02-11
Abstract
Abstract A level detector having good linearity and a high detection efficiency is arranged so as to be small in size and inexpensive to produce, thereby being well suited for use in a semiconductor integrated circuit. The detector employs a common emitter amplifier having two transistors connected in parallel so that odd order harmonic distortion components are mutually eliminated while DC and even order harmonic components appear at the collector thereof. The detector further includes a high impedance load for the two parallel connected transistors. The load is composed of a transistor normally biased in its active region so as to thereby raise the detection efficiency.
Inventors
- 👤 Kenzo Tanabe
- 👤 Junji Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:06
CPC Classifications
H; H03; H03D; H03D1/00; H03D1/14; H03D1/18; G; G01; G01R; G01R19/00; G01R19/165
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
232 words
A level detector comprising: first and second transistors of a first conductivity type, said first and second transistors having their bases connected together; a third transistor of a second conductivity type opposite to that of said first conductivity type; a resistor connected between said third transistor's base and collector; fourth and fifth transistors of said second conductivity type, said fourth and fifth transistors having their collectors connected together; a DC bias circuit operatively connected to said bases of said first and second transistors for supplying a DC bias thereto; wherein said first transistor's collector is connected to said third transistor's collector, said fourth and fifth transistors' bases are respectively connected to said third transistor's collector through separate resistors, said first and second transistors' emitters are respectively connected to a first terminal of a DC power supply through separate resistors, said third and fourth and fifth transistors' emitters are connected to a second terminal of said power supply, said second transistor's collector is connected to said fourth and said fifth transistors' collectors; wherein AC signals having the same amplitude but of opposite polarities are respectively supplied to said fourth and fifth transistors' bases and a level detected output signal is provided at said common collectors of said second and fourth and fifth transistors, and wherein said second transistor is biased in its saturation region when said AC signals are of zero amplitude levels.
Claim 2
Dependent Claim
232 words
A level detector comprising: first and second transistors of a first conductivity type, said first and second transistors having their bases connected together; a third transistor of a second conductivity type opposite to that of said first conductivity type; a resistor connected between said third transistor's base and collector; fourth and fifth transistors of said second conductivity type, said fourth and fifth transistors having their collectors connected together; a DC bias circuit operatively connected to said bases of said first and second transistors for supplying a DC bias thereto; wherein said first transistor's collector is connected to said third transistor's collector, said fourth and fifth transistors' bases are respectively connected to said third transistor's collector through separate resistors, said first and second transistors' emitters are respectively connected to a first terminal of a DC power supply through separate resistors, said third and fourth and fifth transistors' emitters are connected to a second terminal of said power supply, said second transistor's collector is connected to said fourth and said fifth transistors' collectors; wherein AC signals having the same amplitude but of opposite polarities are respectively supplied to said fourth and fifth transistors' bases and a level detected output signal is provided at said common collectors of said second and fourth and fifth transistors, and wherein said second transistor is biased in its saturation region when said AC signals are of zero amplitude levels.
Claim 3
Dependent Claim
75 words
A level detector as recited in claim 1, wherein said DC bias circuit comprises an additional transistor having its base connected to its collector and having its collector connected to said second terminal of said DC power supply through a resistor and having its emitter connnected to said first terminal of said DC power supply through another resistor and having its collector supplying said DC bias to said bases of said first and second transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-04-22 | 1988-10-22 | 1989-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-04-22 | 1992-10-22 | 1993-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-04-22 | 1996-10-22 | 1997-04-23 | $7700.00 | Window Closed / Lapsed |