Fabrication of FETs

Claim 1

A method of forming a field effect transistor which includes a source and drain region formed in the surface of a semiconductor substrate with a channel region therebetween, the method comprising the steps of: forming a pattern of photoresist over the semiconductor substrate which leaves the desired channel region exposed and covers the remainder of the device area in the substrate; implanting impurities into the exposed area of the substrate to form a surface region having a concentration which will set the threshold potential of the device to a desired level; depositing at least one metal over the portion of the semiconductor exposed by the photoresist pattern to establish the boundaries of the gate electrode; removing the photoresist pattern to expose the remainder of the device area; and implanting source and drain regions into the substrate subsequent to the removal of the photoresist utilizing the gate electrode as a mask so as to align the edges of the source and drain regions with the surface region.

Claim 2

A method of forming a field effect transistor which includes a source and drain region formed in the surface of a semiconductor substrate with a channel region therebetween, the method comprising the steps of: forming a pattern of photoresist over the semiconductor substrate which leaves the desired channel region exposed and covers the remainder of the device area in the substrate; implanting impurities into the exposed area of the substrate to form a surface region having a concentration which will set the threshold potential of the device to a desired level; depositing at least one metal over the portion of the semiconductor exposed by the photoresist pattern to establish the boundaries of the gate electrode; removing the photoresist pattern to expose the remainder of the device area; and implanting source and drain regions into the substrate subsequent to the removal of the photoresist utilizing the gate electrode as a mask so as to align the edges of the source and drain regions with the surface region.

Claim 9

A method of forming a field effect transistor which includes a source and drain region of one conductivity type formed in the surface of a semiconductor substrate of opposite conductivity type with a channel region therebetween, the method comprising the steps of: forming over the semiconductor substrate an insulating layer which includes thin portions over the transistor area and thick portions over areas outside the transistor area; forming a layer of polycrystalline silicon over the insulating layer; forming a pattern of photoresist on the polycrystalline silicon layer which leaves exposed the area of the polycrystalline silicon layer over the desired channel region and covers the area of the polycrystalline silicon over the remainder of the device area; isotropically etching a portion of the exposed polycrystalline silicon to undercut the photoresist pattern; implanting impurities through the exposed polycrystalline silicon layer and insulating layer into the substrate to form a surface region of the same conductivity as the substrate which sets the threshold potential of the transistor to a desired level and inhibits source-to-drain punch-through currents; depositing at least one metal onto the exposed polycrystalline silicon; removing the photoresist pattern to expose the remainder of the polycrystalline silicon; heating the structure to form a metal silicide over the surface region; selectively removing the polycrystalline silicon without affecting the metal silicide; and implanting the source and drain regions into the surface of the substrate using the metal silicide and thick insulating portions as a mask so as to align the source and drain regions with the surface region.

Claim 10

A method of forming a field effect transistor which includes a source and drain region of one conductivity type formed in the surface of a semiconductor substrate of opposite conductivity type with a channel region therebetween, the method comprising the steps of: forming over the semiconductor substrate an insulating layer which includes thin portions over the transistor area and thick portions over areas outside the transistor area; forming a layer of polycrystalline silicon over the insulating layer; forming a pattern of photoresist on the polycrystalline silicon layer which leaves exposed the area of the polycrystalline silicon layer over the desired channel region and covers the area of the polycrystalline silicon over the remainder of the device area; isotropically etching a portion of the exposed polycrystalline silicon to undercut the photoresist pattern; implanting impurities through the exposed polycrystalline silicon layer and insulating layer into the substrate to form a surface region of the same conductivity as the substrate which sets the threshold potential of the transistor to a desired level and inhibits source-to-drain punch-through currents; depositing at least one metal onto the exposed polycrystalline silicon; removing the photoresist pattern to expose the remainder of the polycrystalline silicon; heating the structure to form a metal silicide over the surface region; selectively removing the polycrystalline silicon without affecting the metal silicide; and implanting the source and drain regions into the surface of the substrate using the metal silicide and thick insulating portions as a mask so as to align the source and drain regions with the surface region.