Abstract A bipolar ROM having a polysilicon PN junction diode as the matrix element for each bit of storage, wherein the diode is constructed laterally to the associated word line of the array. The word line and diode are implanted with impurities, then metal is deposited on the exposed surfaces of the polysilicon and the structure undergoes a sintering process. A layer of oxide covers the structure and a metal bit line connection is made to the diode P-type section, while the word line and other section of the diode are N-type. P and N type regions may be interchanged, as the polarity of a bit line or word line is a function of drive and sense circuitry. This combination of structure and method allows the use of polysilicon because of the lower sheet resistance and higher speed. Also, the use of PN junction diodes is possible instead of a design requiring Schottky diodes or transistors as matrix elements.
A semiconductor read-only memory comprising: a silicon subtrate; a first addressing means, comprising an N-type polysilicon region in said substrate; a second addressing means, comprising a strip of conductive material on said substrate; a laterial polysilicon PN junction diode, the P-type region being coupled to one of said addressing means, the N-type region being coupled to another of said addressing means, and the PN junction being located laterally between said P-type and N-type regions within said substrate.
Claim 2
Dependent Claim
77 words
A semiconductor read-only memory comprising: a silicon subtrate; a first addressing means, comprising an N-type polysilicon region in said substrate; a second addressing means, comprising a strip of conductive material on said substrate; a laterial polysilicon PN junction diode, the P-type region being coupled to one of said addressing means, the N-type region being coupled to another of said addressing means, and the PN junction being located laterally between said P-type and N-type regions within said substrate.
Claim 3
Dependent Claim
17 words
A semiconductor read-only memory array as in claim 1, wherein said strip of conductive material is aluminum.