US4520553A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for manufacturing an integrated insulated-gate field-effect transistor
Assignee: ITT Inc
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Filing: 1984-05-10
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Granted: 1985-06-04
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Expires: 2004-05-10
Abstract
Abstract A process is described for manufacturing integrated insulated-gate field-effect transistors comprising contacts on both the source region and the drain region which are self-aligned with respect to the gate electrode. In this process the gate area and the areas of the aforementioned regions are defined by means of an oxidation masking layer, and on these regions by employing the oxidation masking layer, there are produced insulator layers which are relatively thick compared to the gate insulator layer.
Inventors
- 👤 Wolfgang Kraft
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:06
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/60; H10P; H10P14/00; H10P14/60; H10P14/61; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0128; H10W10/10; H10W10/13; H10D64/00; H10D64/01; H10D64/017
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
311 words
A process for manufacturing an integrated MIS field effect transistor including source and drain regions introduced into a semiconducting substrate, contacts at the source and drain regions which are self aligned with respect to a gate electrode, the gate electrode being coated with an insulating material by thermal oxidation, contact windows in the insulating material being provided over the source and drain regions, and contacts in the windows attached to the source and drain regions and separated from the gate electrode by the insulating material, said process comprising the steps of: depositing on the surface of said substrate an oxidation masking layer suitable for being used as an ion implantation mask, including depositing a lower partial layer and depositing an upper partial layer, said lower partial layer being selectively etchable relative to said upper partial layer and being capable of being used as said gate insulating material; depositing on said oxidation masking layer a first photoresist mask defining source and drain region areas; removing said oxidation masking layer from said source and drain region areas; implanting ions of the respective conductivity type of source and drain into the surface of said substrate in said source and drain region areas to produce said source and drain regions respectively; producing insulating layers covering said source and drain region areas by thermal oxidation; removing at least said upper partial layer of said oxidation masking layer; covering said source and drain region areas and a gate area with a further oxidation masking layer and defining field areas in the uncovered portions of the substrate; covering the field areas of said substrate lying outside said further oxidation masking layer with a thick oxide layer by way of thermal oxidation; forming contact windows in said insulating layers with the aid of a photoresist mask; and attaching contacts to said source and drain regions in said contact windows.
Claim 2
Dependent Claim
311 words
A process for manufacturing an integrated MIS field effect transistor including source and drain regions introduced into a semiconducting substrate, contacts at the source and drain regions which are self aligned with respect to a gate electrode, the gate electrode being coated with an insulating material by thermal oxidation, contact windows in the insulating material being provided over the source and drain regions, and contacts in the windows attached to the source and drain regions and separated from the gate electrode by the insulating material, said process comprising the steps of: depositing on the surface of said substrate an oxidation masking layer suitable for being used as an ion implantation mask, including depositing a lower partial layer and depositing an upper partial layer, said lower partial layer being selectively etchable relative to said upper partial layer and being capable of being used as said gate insulating material; depositing on said oxidation masking layer a first photoresist mask defining source and drain region areas; removing said oxidation masking layer from said source and drain region areas; implanting ions of the respective conductivity type of source and drain into the surface of said substrate in said source and drain region areas to produce said source and drain regions respectively; producing insulating layers covering said source and drain region areas by thermal oxidation; removing at least said upper partial layer of said oxidation masking layer; covering said source and drain region areas and a gate area with a further oxidation masking layer and defining field areas in the uncovered portions of the substrate; covering the field areas of said substrate lying outside said further oxidation masking layer with a thick oxide layer by way of thermal oxidation; forming contact windows in said insulating layers with the aid of a photoresist mask; and attaching contacts to said source and drain regions in said contact windows.
Claim 3
Dependent Claim
29 words
A process in accordance with claim 1 comprising the steps of: implanting ions of the substrate conductivity type into said field areas prior to said field area covering step.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-06-03 | 1988-12-03 | 1989-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-06-03 | 1992-12-03 | 1993-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-06-03 | 1996-12-03 | 1997-06-04 | $7700.00 | Window Closed / Lapsed |