Semiconductor memory device

Claim 1

A semiconductor memory device comprising: a first MOS transistor and a first load resistor connected in series between a power source voltage and a reference voltage; a second MOS transistor and a second load resistor connected in series between the power source voltage and the reference voltage; a third resistor whose one end is connected to an output node of said first MOS transistor; a fourth resistor whose one end is connected to an output node of said second MOS transistor; first connecting means for interconnecting the output node of said first MOS transistor and the gate of said second MOS transistor; second connecting means for interconnecting the output node of said second MOS transistor and the gate of said first MOS transistor; and third and fourth MOS transistors for data transfer in which said third MOS transistor is connected between a first bit line and the output node of said first MOS transistor, said fourth MOS transistor is connected between a second bit line and the output node of said second MOS transistor, and the gates of said third and fourth MOS transistors are connected to a common word line; wherein the following relations hold ##EQU18## wherein R2: resistance of each of said third and fourth resistors, C1: capacitance on said gate electrode node, C2: capacitance on the output electrode node of each of said first and second MOS transistors, Vo: high level potential on the output electrode node of said first and second MOS transistors, V TN : minimum value of a potential difference appearing between the output nodes of said first and second MOS transistors, with said potential difference the logical "1", "0" states of the output electrode nodes N1 and N2 can return to the steady state; t d : time until the electric current pulse generated due to the incidence of the high energy particles disappears; and t w : minimum value of the pulse width of a write designating signal.