Video display system for displaying symbol-fragments in different orientations

Claim 2

In a raster scanned display, a system for providing symbols comprising: memory means for storing a plurality of symbol-fragments, each of said symbol-fragments being represented in said memory means by a character block consisting of a predetermined number of lines and each of said lines including a predetermined number of bits; a page buffer for storing data representative of said symbol-fragments required for an entire frame of said display; a row buffer coupled between said page buffer and memory means; first circuit means coupled to the input of said memory means for selectively providing said lines for said symbol-fragments in a first order or in a reversed order and; second circuit means coupled to the output of said memory means for selectively providing said bits for said lines in a first order or in a reversed order after said lines are inputted to said memory means by said first circuit means; whereby said symbol-fragments may be used to form symbols for said display with different orientations.

Claim 3

The system defined by claim 1 wherein said first circuit means comprises means for providing first address signals to said memory means to obtain said first order and second address signals to said memory means to obtain said reversed order.

Claim 4

The system defined by claim 2 wherein said second circuit means comprises: first register means for receiving said predetermined number of bits and for arranging them in two groups, one of said groups for providing said first order and the other of said groups for providing said reversed order; and, multiplexing means coupled to said register means for selecting one of said first group and said second group.

Claim 5

The system defined by claim 3 including second register means for providing address signals for said memory means, said second register means coupled to said memory means.

Claim 6

The system defined by claim 4 wherein said second register means includes data for controlling said first circuit means and said multiplexing means, said second register being coupled to said first circuit means and said multiplexing means.

Claim 7

The system defined by claim 5 wherein said first and second registers each provide a delay approximately equal in time to the time required to display one of said lines.

Claim 8

The system defined by claim 1 or 6 including third circuit means for periodically converting said bits to the same binary state so as to cause symbols on said display to blink.

Claim 9

The system defined by claim 1 or 6 including fourth circuit means for converting said bits to their opposite binary state so as to provide a reversed video display.

Claim 10

In a raster scanned display, a system for displaying symbols comprising: a memory for storing a plurality of symbol-fragments, each of said symbol-fragments being represented in said memory by a character block consisting of a predetermined number of lines and each of said lines comprising a predetermined number of bits; a page buffer for storing data representative of said symbol-fragments required for an entire frame of said display; a row buffer coupled between said page buffer and memory means; addressing means coupled to said memory and said row buffer for selectively accessing said lines of said symbol-fragments in a first order or in a reversed order such that each symbol-fragment is read from said memory with either its first line first or its last line first; circuit means coupled to said memory for receiving said bits for each of said lines of said symbol fragments and for selectively providing each of said lines of said symbol fragments with either its most significant bit first or with its least significant bit first; whereby said symbol-fragments may be used to form symbols for said display with different orientations.

Claim 11

In a raster scanned display, a system for displaying symbols comprising: a memory for storing a plurality of symbol-fragments, each of said symbol-fragments being represented in said memory by a character block consisting of a predetermined number of lines and each of said lines comprising a predetermined number of bits; a page buffer for storing data representative of said symbol-fragments required for an entire frame of said display; a row buffer coupled between said page buffer and memory means; addressing means coupled to said memory and said row buffer for selectively accessing said lines of said symbol-fragments in a first order or in a reversed order such that each symbol-fragment is read from said memory with either its first line first or its last line first; circuit means coupled to said memory for receiving said bits for each of said lines of said symbol fragments and for selectively providing each of said lines of said symbol fragments with either its most significant bit first or with its least significant bit first; whereby said symbol-fragments may be used to form symbols for said display with different orientations.

Claim 12

The system defined by claim 9 including a register for supplying addresses to said memory to control said addressing means and circuit means, said register being coupled to said memory, addressing means and circuit means.

Claim 13

The system defined by claim 10 wherein said register and circuit means each provide a delay equal in time to the time required to display one of said lines.