Fabrication methods for high performance lateral bipolar transistors

Claim 1

Method for fabricating a high performance lateral PNP transistor comprising: providing a monocrystalline semiconductor body having a principal surface of N conductivity type and a buries N+ region with an N+ reach-through connecting said buried region to said surface; forming a first P+ polycrystalline silicon layer over said surface so that portions of the layer is in direct contact with the areas designated to be the collector regions; forming an insulator layer upon the top surface of said first polycrystalline silicon layer; patterning said first polycrystalline silicon layer and insulator layer with substantially vertical edges wherein the layer is removed from over areas designated to be the emitter and base regions of said transistor; diffusing N type impurities into the said designated emitter and intrinsic base regions; forming a vertical insulator on said vertical edges of said first polycrystalline silicon layer; heating the structure to fully form the collector region by outdiffusion from said first polycrystalline silicon layer; etching a substantially vertical walled groove in said monocrystalline semiconductor body using the patterned first polycrystalline silicon layer with top insulator and vertical insulator as the etching mask; ion implanting oxygen into the bottom of said groove to form a silicon dioxide region at the bottom of the groove; forming a second P+ polycrystalline silicon layer in said groove; heating the structure to form the P+ emitter region around the side edges of the said P+ polycrystalline silicon filled said groove; and making contact to said transistor wherein said first polycrystalline silicon layer is the collector contact, said second polycrystalline silicon layer is the emitter contact and said N+ reach-through from the surface makes contact through the said buried N+ region to the base region.

Claim 11

The method for fabricating vertical NPN and lateral PNP transistors in the same semiconductor body comprising: providing a P monocrystalline semiconductor substrate; forming a pattern on N+ regions in said substrate; growing an N epitaxial layer on the surface of said substrate having said N+ regions; forming isolated regions of monocrystalline semiconductor in said substrate having said epitaxial layer thereon wherein one of said pattern of said N+ regions is within the isolated regions designated to have NPN and PNP devices formed therein; forming a reach-through region to connect the said one of said N+ regions to the principal surface of said epitaxial layer; dielectrically isolating the designated lateral PNP surface areas from the designated base-emitter region of the NPN surface areas and the said reach-through region; forming a blanket P region in the surface of the region designated as the lateral PNP; forming a first P+ polycrystalline silicon layer over the designated NPN device and designated lateral PNP said isolated regions; forming a insulator layer upon the top surface of said first polycrystalline silicon layer; forming a vertical sided openings in said P+ first polycrystalline layer over the area designated as the emitter and base for said lateral PNP while leaving the polycrystalline silicon layer covering the designated collector area for the said lateral PNP; forming a N region through the said opening designated as the emitter and base which delineates the P collector region of said lateral PNP in said blanket P region; forming a vertical insulator on said vertical sided opening in the lateral PNP region; forming a vertical sided opening in said first P+ polycrystalline layer over the area designated as the emitter and intrinsic base of said vertical NPN while leaving the said P+ polycrystalline silicon layer covering designated base region of the said vertical NPN; heating the structure to simultaneously drive-in the P+ impurities from said first P+ polycrystalline layer to form the extrinsic base region of said vertical NPN and the collector of said lateral PNP; forming the intrinsic P base region in said designated vertical NPN region; forming a vertical insulator on said vertical sided opening in the vertical NPN region; forming a N+ polycrystalline silicon layer over the designated vertical NPN region and driving in N+ impurities from said N+ layer into the said intrinsic P base region to form the N+ emitter region of said vertical NPN; etching a substantially vertical walled groove into said monocrystalline body using the patterned said first P+ polycrystalline silicon layer with top insulator and vertical insulator as the etching mask; ion implanting oxygen into the bottom of said groove to form a silicon dioxide region at the bottom of the groove; forming a second P+ polycrystalline silicon layer in said groove; heating the structure to form the P+ emitter region around the side edges of the said P+ polycrystalline silicon filled said groove; and making contact to said PNP and NPN transistors wherein one portion of said first P+ polycrystalline silicon layer is the PNP collector contact, a second portion of said first P+ polycrystalline silicon layer is the said NPN extrinsic base contact, said reach-through from the surface makes contact through the said N+ buried layer to the base region of said PNP and collector region of said NPN, and said N+ polycrystalline silicon layer is the NPN emitter contact.

Claim 12

The method for fabricating vertical NPN and lateral PNP transistors in the same semiconductor body comprising: providing a P monocrystalline semiconductor substrate; forming a pattern on N+ regions in said substrate; growing an N epitaxial layer on the surface of said substrate having said N+ regions; forming isolated regions of monocrystalline semiconductor in said substrate having said epitaxial layer thereon wherein one of said pattern of said N+ regions is within the isolated regions designated to have NPN and PNP devices formed therein; forming a reach-through region to connect the said one of said N+ regions to the principal surface of said epitaxial layer; dielectrically isolating the designated lateral PNP surface areas from the designated base-emitter region of the NPN surface areas and the said reach-through region; forming a blanket P region in the surface of the region designated as the lateral PNP; forming a first P+ polycrystalline silicon layer over the designated NPN device and designated lateral PNP said isolated regions; forming a insulator layer upon the top surface of said first polycrystalline silicon layer; forming a vertical sided openings in said P+ first polycrystalline layer over the area designated as the emitter and base for said lateral PNP while leaving the polycrystalline silicon layer covering the designated collector area for the said lateral PNP; forming a N region through the said opening designated as the emitter and base which delineates the P collector region of said lateral PNP in said blanket P region; forming a vertical insulator on said vertical sided opening in the lateral PNP region; forming a vertical sided opening in said first P+ polycrystalline layer over the area designated as the emitter and intrinsic base of said vertical NPN while leaving the said P+ polycrystalline silicon layer covering designated base region of the said vertical NPN; heating the structure to simultaneously drive-in the P+ impurities from said first P+ polycrystalline layer to form the extrinsic base region of said vertical NPN and the collector of said lateral PNP; forming the intrinsic P base region in said designated vertical NPN region; forming a vertical insulator on said vertical sided opening in the vertical NPN region; forming a N+ polycrystalline silicon layer over the designated vertical NPN region and driving in N+ impurities from said N+ layer into the said intrinsic P base region to form the N+ emitter region of said vertical NPN; etching a substantially vertical walled groove into said monocrystalline body using the patterned said first P+ polycrystalline silicon layer with top insulator and vertical insulator as the etching mask; ion implanting oxygen into the bottom of said groove to form a silicon dioxide region at the bottom of the groove; forming a second P+ polycrystalline silicon layer in said groove; heating the structure to form the P+ emitter region around the side edges of the said P+ polycrystalline silicon filled said groove; and making contact to said PNP and NPN transistors wherein one portion of said first P+ polycrystalline silicon layer is the PNP collector contact, a second portion of said first P+ polycrystalline silicon layer is the said NPN extrinsic base contact, said reach-through from the surface makes contact through the said N+ buried layer to the base region of said PNP and collector region of said NPN, and said N+ polycrystalline silicon layer is the NPN emitter contact.