History memory control system

Claim 2

A history memory control system in a data processing system, comprising: a history memory for serially collecting and storing internal state information; a freeze control circuit connected to said history memory, for inhibiting update of said history memory and releasing said history memory; condition sensing means, connected to said freeze control circuit, for sending first freeze and release signals in accordance with predetermined hardware conditions to said freeze control circuit; a microprogram processing system for executing micro-instructions which include a control field for history memory freeze and release micro-instructions; decoding means, connected to said freeze control circuit and said microprogram processing system, for decoding the control field in the micro-instructions and sending second freeze and release signals to said freeze control circuit when the history memory freeze and release micro-instructions are decoded, thereby said history memory is controlled both when the predetermined hardware conditions are generated and when history memory freeze and release micro-instructions are executed.

Claim 3

A history memory control system according to claim 1, wherein said decoding means comprises a decoder, connected to said freeze control circuit and said microprogram processing system, which decodes the control field in the micro-instructions and generates the second freeze and release signals, wherein said microprogram processing system generates a valid signal as each of the micro-instructions becomes available to said decoder and the data processing system generates a write enable signal, and wherein said freeze control circuit comprises: a first gate circuit, connected to said microprogram processing system and said decoder, for ANDing the valid signal and the second freeze signal and generating an output; a second gate circuit, connected to said microprogram processing system and said decoder, for ANDing the valid signal and the second release signal and generating an output; a third gate circuit, connected to said condition sensing means and said first gate circuit, for ORing the first freeze signal and the output of said first gate circuit and generating a set signal; a fourth gate circuit, connected to said condition sensing means and said second gate circuit, for ORing the first release signal and the output of said second gate circuit and generating a reset signal; a flip-flop, connected to receive the set signal from said third gate circuit and the reset signal from said fourth gate circuit, outputting a freeze history latch signal; and a fifth gate circuit, connected to said flip-flop and to receive the write enable signal, for controlling the write enable signal to said history memory using the freeze history latch signal of said flip-flop.

Claim 4

A history memory control system according to claim 1 or claim 2, wherein said microprogram processing system comprises: a control memory for storing micro-instructions; and a pipeline structure having stages, connected to said decoding means and said control memory, for executing the micro-instructions read from the control memory, whereby the control field for history memory freeze and release micro-instructions is decoded at one of the stages.