Digital character display

Claim 2

A digital character display system for a raster scan display unit, said system comprising: a control unit for receiving control information characters from an associated source, said control unit including means for generating vertical and horizontal sync timing signals to be coupled to said display; first memory means having an input coupled to said control unit for storing multi-bit controller characters, each character having a first multi-bit portion specifying font character addresses and a second multi-bit portion specifying character attributes, said first memory means having an output; second memory means coupled to a first multi-bit portion output of said first memory means and containing a plurality of multi-bit font characters each addressable by a corresponding one of said first multi-bit portions of said multi-bit controller characters; shift register means having an input coupled to said second memory means for successively storing font characters individually output from said second memory means and for converting said characters from parallel to serial form, said shift register means having an output; and video control means having a first input coupled to the output of said shift register for converting said characters output from said shift register means to video information signals, said video control means having a second input for receiving the character attribute multi-bit portion of each controller character output from said first memory means for modifying said video information signals.

Claim 5

The invention of claim 1 wherein said system further includes means for synchronizing the arrival of said font characters and said character attribute portions of said controller characters at said video control means.

Claim 6

The invention of claim 1 wherein said control until further includes means coupled to said second input of said video control means for generating control signals for said video control means.

Claim 7

The invention of claim 1 wherein said first and second memory means have an addressing cycle and said shift register means has a load cycle; and wherein said control unit further includes clock circuit means for controlling the addressing cycle of said first memory means and said second memory means and the load cycle of said shift register means.

Claim 8

The invention of claim 5 wherein said clock circuit means includes means responsive to a control information character from the associated source for selecting one of two clock cycles having different periods to enable said display system to selectively operate in a high resolution mode in which all bits of each font character are shifted out of said shift register means and a text mode in which less than all bits of each font character are shifted out of said shift register means.

Claim 9

The invention of claim 1 wherein one bit of said second multi-bit portion specifies the character attribute of overall character intensity, and wherein said video control means includes means responsive to the intensity attribute bit for establishing the display intensity of the corresponding font character.

Claim 10

The invention of claim 7 wherein said establishing means includes a collector-emitter coupled paired transistor circuit having a pair of transistors, each transistor having a base, and a flip flop having a data input supplied with the intensity attribute bit and an output coupled to the base of one of the transistors in said paired transistor circuit.

Claim 11

The invention of claim 2 wherein said method includes the step of temporarily storing said multi-bit screen attribute portion of said controller character until said font character has been serially supplied to the video signal generator.

Claim 12

The invention of claim 2 wherein one of said at least one screen attributes is overall character intensity, and wherein said step of controlling includes the steps of establishing the display intensity of said font character in accordance with the intensity attribute bit of said second multi-bit screen attribute portion of said controller character.

Claim 15

The invention of claim 11 wherein said step of repeating includes the steps of selecting a first rate when displaying text information and selecting a second rate when displaying graphics information.

Claim 16

The invention of claim 12 wherein said first rate is higher than said second rate.

Claim 19

The invention of claim 14 wherein said delaying means comprises a plurality of serially coupled latch means.

Claim 20

A digital character display system for a raster scanned unit, said system comprising: a control unit for receiving control information characters from an associated source, said control unit including means for generating vertical and horizontal sync timing signals to be coupled to said display; first memory means having an input coupled to said control unit for storing multi-bit controller characters, each character having a first multi-bit portion specifying font character addresses and a second multi-bit portion specifying character attributes, said first memory means having an output; second memory means coupled to a first multi-bit portion output of said first memory means and containing a plurality of multi-bit font characters each addressable by a corresponding one of said first multi-bit portions of said multi-bit controller characters; shift register means having an input coupled to said second memory means for successively storing font characters individually output from said second memory means and for converting said characters from parallel to serial form, said shift register means having an output; video control means having a first input coupled to the output of said shift register for converting said characters output from said shift register means to video information signals, said video control means having a second input for receiving the character attribute multi-bit portion of each controller character output from said first memory means for modifying said video information signals; and means for synchronizing the arrival of said font characters and said character attribute portions of said controller characters at said video control means, said synchronizing means including a first latch means coupled between said first memory means and said second memory means, a second latch means coupled between said second memory means and said shift register means, said first and second latch means providing temporary intermediate storage of said multi-bit portion of said controller characters and said font characters, respectively, and means coupled between said first memory means and said video control means for delaying said second multi-bit portion of said controller characters in order to synchronize the first and second portions for proper input to the video control means.

Claim 21

A digital character display system for a raster scanned unit, said system comprising: a control unit for receiving control information characters from an associated source, said control unit including means for generating vertical and horizontal sync timing signals to be coupled to said display; first memory means having an input coupled to said control unit for storing multi-bit controller characters, each character having a first multi-bit portion specifying font character addresses and a second multi-bit portion specifying character attributes, said first memory means having an output; second memory means coupled to a first multi-bit portion output of said first memory means and containing a plurality of multi-bit font characters each addressable by a corresponding one of said first multi-bit portions of said multi-bit controller characters; shift register means having an input coupled to said second memory means for successively storing font characters individually output from said second memory means and for converting said characters from parallel to serial form, said shift register means having an output; video control means having a first input coupled to the output of said shift register for converting said characters output from said shift register means to video information signals, said video control means having a second input for receiving the character attribute multi-bit portion of each controller character output from said first memory means for modifying said video information signals; and means for synchronizing the arrival of said font characters and said character attribute portions of said controller characters at said video control means, said synchronizing means including a first latch means coupled between said first memory means and said second memory means, a second latch means coupled between said second memory means and said shift register means, said first and second latch means providing temporary intermediate storage of said multi-bit portion of said controller characters and said font characters, respectively, and means coupled between said first memory means and said video control means for delaying said second multi-bit portion of said controller characters in order to synchronize the first and second portions for proper input to the video control means.