Digital signal processing circuitry for a color-television receiver

Claim 2

Digital signal processing circuitry comprising: a multiplier circuit having first inputs for receiving two demodulated digital color difference signals, second inputs for receiving a color-saturation signal, and third inputs for receiving multiplier factors, and having outputs, said multiplier providing a first multiplied pair of signals at one output, a first one of said first pair of signals corresponding to the product of one of said color difference signals, said color-saturation signal and a first one of said multiplier factors, a second one of said first pair of signals corresponding to the product of the other of said color difference signals, said color-saturation signal and a second one of said multiplier factors, said multiplier providing a second multiplexed pair of signals at a second output, a first one of said second pair of signals corresponding to the product of said one of said color difference signals, said color-saturation signal and a third one of said multiplier factors, a second one of said second pair of signals corresponding to the product of said other of said color difference signals, said color-saturation signal and a fourth one of said multiplier factors; a first adder having first inputs coupled to said multiplier and second inputs for receiving a digital luminance signal, said first adder adding said first pair of multiplexed signals and said digital luminance signal to provide signals at outputs; a second adder having first inputs coupled to said multiplier and second inputs for receiving said digital luminance signal, said second adder adding said second pair of multiplexed signals and said digital luminance signal to provide signals at outputs.

Claim 3

A signal processing circuitry in accordance with claim 1 comprising: a first digital to analog converter having digital inputs coupled to said first adder outputs and having analog outputs; and a second digital to analog converter having digital inputs coupled to said second adder outputs and having analog outputs.

Claim 4

Signal processing circuitry in accordance with claim 2, wherein said multiplier circuit comprises a first multiplier for receiving said color-saturation signal and said plurality of multiplier factors and providing first, second, third and fourth products of said color-saturation signal with said first, second, third and fourth multiplier factors, respectively; and a second multiplier for multiplying said first color difference signal with each of said first and second products and said second color difference signal with each of said third and fourth products.

Claim 5

Signal processing circuitry in accordance with claim 1 comprising: a memory for storing said first, second, third and fourth multiplier factors and having outputs coupled to said multiplier for supplying thereto said first, second, third and fourth multiplier factors.

Claim 6

Signal processing circuitry in accordance with claim 2 comprising: a memory for storing said first, second, third and fourth multiplier factors and having outputs coupled to said multiplier for supplying thereto said first, second, third and fourth multiplier factor.

Claim 7

Signal processing circuitry in accordance with claim 3 comprising: a memory for storing said first, second, third and fourth multiplier factors and having outputs coupled to said multiplier for supplying thereto said first, second, third and fourth multiplier factor.

Claim 8

Signal processing circuitry in accordance with claim 4, wherein said memory has an input whereby said first, second, third and fourth multiplier factors may be varied or adjusted.

Claim 9

Signal processing circuitry in accordance with claim 5, wherein said memory has an input whereby said first, second, third and fourth multiplier factors may be varied or adjusted.

Claim 10

Signal processing circuitry in accordance with claim 6, wherein said memory has an input whereby said first, second, third and fourth multiplier factors may be varied or adjusted.

Claim 11

Signal processing circuitry in accordance with claim 2 comprising: a third digital to analog converter for converting said digital luminance signal to an analog signal; and an R-G-B matrix having inputs coupled to said first, second, and third digital to analog converters.

Claim 12

Signal processing circuitry in accordance with claim 10, wherein said multiplier circuit comprises a first multiplier for receiving said color-saturation signal and said plurality of multiplier factors and providing first, second, third and fourth products of said color-saturation signal with said first, second, third and fourth multiplier factors, respectively; and a second multiplier for multiplying said first color difference signal with each of said first and second products and said second color difference signal with each of said third and fourth products.

Claim 13

Signal processing circuitry in accordance with claim 10 comprising: a memory for storing said first, second, third and fourth multiplier factors and having outputs coupled to said multiplier for supplying thereto said first, second, third and fourth multiplier factor.

Claim 14

Signal processing circuitry in accordance with claim 11 comprising: a memory for storing said first, second, third and fourth multiplier factors and having outputs coupled to said multiplier for supplying thereto said first, second, third and fourth multiplier factor.

Claim 15

Signal processing circuitry in accordance with claim 12, wherein said memory has an input whereby said first, second, third and fourth multiplier factors may be varied or adjusted.

Claim 16

Signal processing circuitry in accordance with claim 13, wherein said memory has an input whereby said first, second, third and fourth multiplier factors may be varied or adjusted.

Claim 17

Signal processing circuitry in accordance with claim 4, wherein said memory is a read only memory.

Claim 18

Signal processing circuitry in accordance with claim 5, wherein said memory is a read only memory.

Claim 19

Signal processing circuitry in accordance with claim 6, wherein said memory is a read only memory.

Claim 20

Signal processing circuitry in accordance with claim 12, wherein said memory is a read only memory.

Claim 21

Signal processing circuitry in accordance with claim 13, wherein said memory is a read only memory.

Claim 22

Signal processing circuitry in accordance with claim 1, wherein said multiplier provides a third multiplexed pair of signals at a third output, a first one of said third pair of signals corresponding to the product of said one color difference signal, said color-saturation signal and a fifth multiplier factor, a second one of said third pair of signals corresponding to the product of said other of said color difference signals, said color-saturation signal and a sixth multiplier factor; and said circuitry further comprises a third adder having first inputs coupled to said multiplier and second inputs for receiving said digital luminance signal, said third adder adding said third pair of multiplexed signals and said luminance signal to provide signals at outputs.

Claim 23

A signal processing circuitry in accordance with claim 21 comprising: a first digital to analog converter having digital inputs coupled to said first adder outputs and having analog outputs; a second digital to analog converter having digital inputs coupled to said second adder outputs and having analog outputs; and a third digital to analog converter having digital inputs coupled to said third adder outputs and having analog outputs.

Claim 24

A digital integrated circuit for a color-television receiver with digital signal processing circuitry comprising: a first multiplier having first inputs for receiving for multiplying a first demodulated digital color difference signal with second digital signals and a second demodulated digital color difference signal with said second digital signals to provide three multiplexed signal pair outputs; a second multiplier for multiplying a color-saturation signal with each of a plurality of multiplier factors to provide said second digital signals; a memory storing each of said plurality of multiplier factors and coupled to said second multiplier for supplying thereto said plurality of multiplier factors, said multiplier factors being defined as follows: b'=s(b-y)b1, b"=s(r-y)b2, g'=s(b-y)g1, g"=s(r-y)g2, r'=s(b-y)r1, and r"=s(r-y)r2 where s is the color-saturation signal, b-y is the first color difference signal, r-y is the second color difference signal b' and b" are a first pair of said three multiplexed signal pair outputs, g' and g" are a second pair of said three multiplexed signal pair outputs, r' and r" are a third pair of said multiplexed signal pair outputs, and b1, b2, g1, g2, r1 and r2 are said multiplier factors; a first adder for adding said b' and b" signal pair with a digital luminance signal; a first digital to analog converter having its digital input coupled to the output of said first adder for providing an analog blue signal; a second adder for adding said g' and g" signal pair with said digital luminance signal; a second digital to analog converter having its digital input coupled to the output of said second adder for providing an analog green signal; a third adder for adding said r' and r" signal pair with said digital luminance signal; and a third digital to analog converter having its digital input coupled to the output of said third adder for providing an analog red signal.

Claim 25

A digital integrated circuit for a color-television receiver with digital signal processing circuitry comprising: a first multiplier having first inputs for receiving for multiplying a first demodulated digital color difference signal with second digital signals and a second demodulated digital color difference signal with said second digital signals to provide three multiplexed signal pair outputs; a second multiplier for multiplying a color-saturation signal with each of a plurality of multiplier factors to provide said second digital signals; a memory storing each of said plurality of multiplier factors and coupled to said second multiplier for supplying thereto said plurality of multiplier factors, said multiplier factors being defined as follows: b'=s(b-y)b1, b"=s(r-y)b2, g'=s(b-y)g1, g"=s(r-y)g2, r'=s(b-y)r1, and r"=s(r-y)r2 where s is the color-saturation signal, b-y is the first color difference signal, r-y is the second color difference signal b' and b" are a first pair of said three multiplexed signal pair outputs, g' and g" are a second pair of said three multiplexed signal pair outputs, r' and r" are a third pair of said multiplexed signal pair outputs, and b1, b2, g1, g2, r1 and r2 are said multiplier factors; a first adder for adding said b' and b" signal pair with a digital luminance signal; a first digital to analog converter having its digital input coupled to the output of said first adder for providing an analog blue signal; a second adder for adding said g' and g" signal pair with said digital luminance signal; a second digital to analog converter having its digital input coupled to the output of said second adder for providing an analog green signal; a third adder for adding said r' and r" signal pair with said digital luminance signal; and a third digital to analog converter having its digital input coupled to the output of said third adder for providing an analog red signal.

Claim 26

A digital integrated circuit in accordance with claim 23, wherein said multiplier factors are permanently stored in said memory.

Claim 27

A digital integrated circuit in accordance with claim 23, wherein said multiplier factors may be adjusted during operation of said receiver in accordance with a third digital signal.

Claim 28

A digital integrated circuit in accordance with claim 24, wherein said multiplier factors may be adjusted during operation of said receiver in accordance with a third digital signal.

Claim 29

A digital integrated circuit in accordance with claim 23, for driving a color picture tube with an analog luminance signal Y where Y=0.3R+0.5G+0.11B, wherein said multiplier factors have the following decimal numerical values: b1=1/b*, b2=0, r1=0, r2=1/r*, g1=-0.19b*, and g2=-0.51/r* where b* and r* are factors by which the blue- and red-minus-luminance signals, respectively, are multiplied at the transmitting color signal source in accordance with a predetermined color television standard.

Claim 30

A digital integrated circuit in accordance with claim 27, wherein said standard is the PAL or NTSC standard and b*=0.493 and r*=0.877.

Claim 31

A digital integrated circuit in accordance with claim 27, wherein said standard is the SECAM standard and b*=1.5 and r*=-1.9.

Claim 32

A digital integrated circuit in accordance with claim 23 for driving a color picture tube having a color loci different from that of a conventional color picture tube with an analog luminance signal Y where Y=0.3R'R+0.59G'G+0.11B'B, wherein said multiplier factors have the following decimal numerical values: b1=1/b*, b2=0, g1=-0.19B'/G'b*, g2=-0.51R'/G'r*, r1=0, and r2=1/r* where b* and r* are factors by which the blue-minus-luminance and red-minus-luminance signals, respectively, are multiplied at the source of color signals in accordance with a predetermined color television standard.

Claim 33

A digital integrated circuit in accordance with claim 30, wherein said standard is the PAL or NTSC standard and b*=0.493 and r*=0.877.

Claim 34

A digital integrated circuit in accordance with claim 30, wherein said standard is the SECAM standard and b*=1.5 and r*=-1.9.

Claim 35

A digital integrated circuit for a color-television receiver with digital signal processing circuitry comprising: a first multiplier having first inputs for receiving for multiplying a first demodulated digital color difference signal with second digital signals and a second demodulated digital color difference signal with said second digital signals to provide two multiplexed signal pair outputs; a second multiplier for multiplying a color-saturation signal with each of a plurality of multiplier factors to provide said second digital signals; a memory storing each of said plurality of multiplier factors and coupled to said second multiplier for supplying thereto said plurality of multiplier factors, said multiplier factors being defined as follows: b'=s(b-y)b1, b"=s(r-y)b2, r'=s(b-y) r1, and r"=s(r-y)r2 where s is the color-saturation signal, b-y is the first color difference signal, r-y is the second color difference signal b' and b" are a first pair of said two multiplexed signal pair outputs, r' and r" are a second pair of said multiplexed signal pair outputs, and b1, b2, r1 and r2 are said multiplier factors; a first adder for adding said b' and b" signal pair; a first digital to analog converter having its digital input coupled to the output of said first adder for providing an analog B-Y signal; a second digital to analog converter receiving a digital luminance signal at its digital input for providing an analog luminance signal; a second adder for adding said r' and r" signal pair; and a third digital to analog converter having its digital input coupled to the output of said second adder for providing an analog R-Y signal.

Claim 36

A digital integrated circuit for a color-television receiver with digital signal processing circuitry comprising: a first multiplier having first inputs for receiving for multiplying a first demodulated digital color difference signal with second digital signals and a second demodulated digital color difference signal with said second digital signals to provide two multiplexed signal pair outputs; a second multiplier for multiplying a color-saturation signal with each of a plurality of multiplier factors to provide said second digital signals; a memory storing each of said plurality of multiplier factors and coupled to said second multiplier for supplying thereto said plurality of multiplier factors, said multiplier factors being defined as follows: b'=s(b-y)b1, b"=s(r-y)b2, r'=s(b-y) r1, and r"=s(r-y)r2 where s is the color-saturation signal, b-y is the first color difference signal, r-y is the second color difference signal b' and b" are a first pair of said two multiplexed signal pair outputs, r' and r" are a second pair of said multiplexed signal pair outputs, and b1, b2, r1 and r2 are said multiplier factors; a first adder for adding said b' and b" signal pair; a first digital to analog converter having its digital input coupled to the output of said first adder for providing an analog B-Y signal; a second digital to analog converter receiving a digital luminance signal at its digital input for providing an analog luminance signal; a second adder for adding said r' and r" signal pair; and a third digital to analog converter having its digital input coupled to the output of said second adder for providing an analog R-Y signal.

Claim 37

A digital integrated circuit in accordance with claim 33, wherein said multiplier factors have the following values: b1=cos α b2=sin α r1=-sin α r2=cos α where α is the phase angle between the digital blue-minus-luminance signal and a color burst signal.

Claim 38

A digital integrated circuit in accordance with claim 34, wherein α can be set by the user of the receiver.

Claim 39

A digital integrated circuit in accordance with claim 34, wherein α is automatically adjusted.

Claim 40

A digital integrated circuit in accordance with claim 33, wherein said B-Y, R-Y and luminance signals are coupled to an analog R-G-B matrix.

Claim 41

Signal processing circuitry in accordance with claim 7, wherein said multiplier factor may be adjusted in accordance with a Vertical Interval Reference signal.

Claim 42

Signal processing circuitry in accordance with claim 8, wherein said multiplier factor may be adjusted in accordance with a Vertical Interval Reference signal.

Claim 43

Signal processing circuitry in accordance with claim 9, wherein said multiplier factor may be adjusted in accordance with a Vertical Interval Reference signal.