Optically coupled differential data link

Claim 1

A binary digital data link apparatus comprising: first and second conductive transmission lines each having a transmitter end and a receiver end; differential transmitter means connected to said transmission lines and having first and second data input connections, said transmitter means being responsive to predetermined combinations of first and second input logic levels at each of said first and second data input connections to provide predetermined electrical conditions at the transmitter ends of said transmission lines; said transmitter means comprising a first solid state switching network connected between a voltage source and said first transmission line, a second solid state switching network connected between a voltage source and said second transmission line, input logic means responsive to said predetermined combinations of input logic levels for controlling said first and second networks so as to provide electrical current flow to and from said receiver means in a first directional sense corresponding to a first of said predetermined combinations and in a second directional sense corresponding to a second of said predetermined combinations; said receiver means comprising first and second oppositely oriented current regulator means, responsive to electrical conditions on said transmission lines for directing said current through first or second receiver paths, and first and second current to voltage level means responsive to said current in said first and second paths, respectively, for providing said output logic levels; and said logic means comprising first, second, and third coincidence gates, said first gate being responsive to coincidence of a first of said input logic levels and a predetermined output of said third gate, said second gate being responsive to coincidence of a second of said input logic levels and a predetermined output of said third gate, and said third gate being responsive to coincidences of predetermined ones of said input logic levels at said first and second data input connections.