Patent US2928423A successfully refreshed from Google Patents.
US4569064A
Expired / Lapsed
US
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Device for recovery of clock frequency in digital transmission
Assignee: Thales SA
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Filing: 1983-03-14
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Granted: 1986-02-04
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Expires: 2003-03-14
Abstract
Abstract The device for recovery of the clock frequency of a digital signal comprises a rectifier, a filter having a very narrow bandwidth coupled to the first input of a phase comparator of analog type, a controlled oscillator, the output of which delivers the recovered clock signal and is coupled to the second input of the phase comparator via a low-pass filter. The output of the phase comparator is connected to the input of a loop filter, the output of which is connected to the control input of the oscillator.
Inventors
- 👤 Claude Collin
- 👤 Joel Faydit
- 👤 Herve Pinsard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:13
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/027; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
178 words
A device for recovery of the clock frequency of a signal in digital transmission, wherein said device comprises an analog rectifying circuit receiving said signal and having an output for causing a component to appear in the signal at the frequency of the clock rate, the output of said rectifying circuit being connected to a filtering circuit of very narrow bandwidth having an output, said filtering circuit including a low pass input filter coupled to a filter having a narrow bandwidth, and a quartz oscillator circuit having a phase control input and an output, said oscillator circuit being controlled by a phase-control loop, said loop comprising a phase comparator of the analog type having two inputs respectively coupled to the output of the filtering circuit and to the output of the oscillator, and having an output coupled to the phase control input of said oscillator, said phase comparator being adapted to deliver a zero error signal when the signals on its two inputs have a predetermined phase relationship or when output signal of the filtering circuit is zero.
Claim 2
Independent Claim
178 words
A device for recovery of the clock frequency of a signal in digital transmission, wherein said device comprises an analog rectifying circuit receiving said signal and having an output for causing a component to appear in the signal at the frequency of the clock rate, the output of said rectifying circuit being connected to a filtering circuit of very narrow bandwidth having an output, said filtering circuit including a low pass input filter coupled to a filter having a narrow bandwidth, and a quartz oscillator circuit having a phase control input and an output, said oscillator circuit being controlled by a phase-control loop, said loop comprising a phase comparator of the analog type having two inputs respectively coupled to the output of the filtering circuit and to the output of the oscillator, and having an output coupled to the phase control input of said oscillator, said phase comparator being adapted to deliver a zero error signal when the signals on its two inputs have a predetermined phase relationship or when output signal of the filtering circuit is zero.
Claim 3
Dependent Claim
70 words
A device according to claim 1, wherein the oscillator is frequency-controlled by a varactor having a high internal resistance and wherein the phase loop comprises a loop filter with a high-value capacitor which discharges slowly through the varactor at the time of interruptions of transmission, the duration of drift of the recovered clock signal being only a fraction of a period during interruption intervals of the order of one second.
Claim 4
Dependent Claim
38 words
A device according to claim 2, wherein said loop has a high loop gain so as to permit a rapid return of the clock signal phase to its nominal value without any discontinuity after an interruption of transmission.
Claim 5
Dependent Claim
33 words
A device according to claim 1, wherein the rectifying circuit comprises two linear amplifiers in parallel having inverted outputs, and a full-wave diode rectifier having inputs connected the inverted output of the amplifiers.
Claim 6
Dependent Claim
47 words
A device according to claim 1, wherein the filtering circuit comprises said low-pass input filter followed by said filter which is centered on the frequency of the clock rate and has a very narrow band, on the order of 10 -4 with respect to the clock frequency.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-03 | 1989-08-05 | 1990-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-03 | 1993-08-05 | 1994-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-03 | 1997-08-05 | 1998-02-04 | $7700.00 | Window Closed / Lapsed |