Output circuit having decreased interference between output terminals

Claim 2

An output circuit responsive to a control signal for selectively providing an output signal at its output terminal in accordance with an input logic signal, said circuit comprising: a first field effect transistor having first, second, and third terminals and conducting between its first and second terminals in accordance with a potential applied to its third terminal, said third terminal comprising a gate electrode for receiving a voltage corresponding to said input logic signal, said second terminal being coupled to a relatively low voltage point and said first terminal being coupled to an output terminal of said output circuit; a voltage generating source for providing a potential lower than a potential at said low voltage point; and a second insulated gate field effect transistor having first, second, and third terminals and conducting between its first and second terminals in accordance with a potential applied to its third terminal, said third terminal of said second transistor comprising a gate electrode for receiving said control signal, said second terminal of said second transistor being coupled to said voltage generating source and said first terminal of said second transistor being coupled to said gate electrode of said first transistor, a channel length of said first transistor being shorter than a channel length of said second transistor.

Claim 3

An output circuit as claimed in claim 1, said voltage generating source comprising a capacitance means and a plurality of field effect transistors, each transistor including first, second, and third terminals and conducting between its first and second terminals in accordance with a potential at its third terminal, the third terminal of each said transistor comprising a gate electrode, said plurality of field effect transistors comprising: a first rectifier field effect transistor having its second and third terminals connected to said lower voltage point and its first terminal connected to a terminal to which a clock signal is applied through said capacitance means; a second rectifier field effect transistor having its second and third terminals connected to said first terminal of said first rectifier field effect transistor and its first terminal connected to a low-level voltage point; and a clamp field effect transistor having its first terminal connected to said lower voltage point and its second and third terminals connected to a low-level voltage point.

Claim 4

An output circuit responsive to a control signal for selectively providing an output signal at its output terminal in accordance with an input logic signal, said circuit including a first plurality of field effect transistors, each of said transistors having first, second, and third terminals, each of said transistors conducting between its first and second terminals in accordance with a potential applied to its third terminal, the third terminal of each of said transistors comprising a gate electrode, said circuit including a first low potential point, a second low potential point, and a voltage generating source for providing a lower potential to said second low potential point than exists at said first low potential point, said plurality of field effect transistors comprising: a first field effect transistor connected between an output terminal and said first low potential point and to which a first control signal is applied to its third terminal; a second field effect transistor having its first terminal connected to said third terminal of said first transistor and its second terminal connected to said second low potential point, a second control signal being supplied to its third terminal; a pull up field effect transistor connected between a relatively high voltage point and said output terminal and to which a signal in complementary relation with said first control signal applied to said third terminal of said first transistor is applied to its third terminal; and a third field effect transistor connected between said third terminal of said pull up transistor and said second low potential point and to which said second control signal supplied to said third terminal of said second transistor is supplied to its third terminal.

Claim 5

An output circuit responsive to a control signal for selectively providing an output signal at its output terminal in accordance with an input logic signal, said circuit including a first plurality of field effect transistors, each of said transistors having first, second, and third terminals, each of said transistors conducting between its first and second terminals in accordance with a potential applied to its third terminal, the third terminal of each of said transistors comprising a gate electrode, said circuit including a first low potential point, a second low potential point, and a voltage generating source for providing a lower potential to said second low potential point than exists at said first low potential point, said plurality of field effect transistors comprising: a first field effect transistor connected between an output terminal and said first low potential point and to which a first control signal is applied to its third terminal; a second field effect transistor having its first terminal connected to said third terminal of said first transistor and its second terminal connected to said second low potential point, a second control signal being supplied to its third terminal; a pull up field effect transistor connected between a relatively high voltage point and said output terminal and to which a signal in complementary relation with said first control signal applied to said third terminal of said first transistor is applied to its third terminal; and a third field effect transistor connected between said third terminal of said pull up transistor and said second low potential point and to which said second control signal supplied to said third terminal of said second transistor is supplied to its third terminal.

Claim 6

An output circuit as claimed in claim 3, said voltage generating source comprising a capacitance means and a second plurality of field effect transistors, each transistor including first, second, and third terminals and conducting between its first and second terminals in accordance with a potential at its third terminal, the third terminal of each said transistor comprising a gate electrode, said second plurality of field effect transistors comprising: a first rectifier field effect transistor having its second and third terminals connected to said second low potential point and its first terminal connected to a terminal to which a clock signal is applied through said capacitance means; a second rectifier field effect transistor having its second and third terminals connected to said first terminal of said first rectifier field effect transistor and its first terminal connected to a low-level voltage point; and a clamp field effect transistor having its first terminal connected to said second low potential point and its second and third terminals connected to a low-level voltage point.

Claim 7

An output circuit as claimed in claim 3, wherein channel lengths of said first transistor and said pull up transistor are shorter than channel lengths of said second and third transistors.

Claim 8

An output circuit system in which the output terminals of output circuit components of a plurality of semiconductor integrated circuits are connected in common with each other, these common terminals serving as output terminals of the system, said system including a voltage generating source, each of the output circuit components of said plurality of semiconductor integrated circuits including a first plurality of field effect transistors, each of said transistors having first, second, and third terminals, each of said transistors conducting between its first and second terminals in accordance with a potential applied to its third terminal, said third terminal of each of said transistors comprising a gate electrode, said first plurality of field effect transistors comprising: a first transistor having its first electrode connected to the output terminals of said system, which is connected by a load element to a relatively high voltage point, and its second electrode connected to a relatively low voltage point, logic voltage being supplied to its third terminal; and a second transistor having its first terminal connected to said third terminal of said first transistor and its second electrode connected to a voltage point lower than said relatively low voltage point, a chip select signal being supplied to its third terminal.

Claim 9

An output circuit system in which the output terminals of output circuit components of a plurality of semiconductor integrated circuits are connected in common with each other, these common terminals serving as output terminals of the system, said system including a voltage generating source, each of the output circuit components of said plurality of semiconductor integrated circuits including a first plurality of field effect transistors, each of said transistors having first, second, and third terminals, each of said transistors conducting between its first and second terminals in accordance with a potential applied to its third terminal, said third terminal of each of said transistors comprising a gate electrode, said first plurality of field effect transistors comprising: a first transistor having its first electrode connected to the output terminals of said system, which is connected by a load element to a relatively high voltage point, and its second electrode connected to a relatively low voltage point, logic voltage being supplied to its third terminal; and a second transistor having its first terminal connected to said third terminal of said first transistor and its second electrode connected to a voltage point lower than said relatively low voltage point, a chip select signal being supplied to its third terminal.

Claim 10

An output circuit as claimed in claim 6, said voltage generating source comprising a capacitance means and a second plurality of field effect transistors, each transistor including first, second, and third terminals and conducting between its first and second terminals in accordance with a potential at its third terminal, the third terminal of each said transistor comprising a gate electrode, said second plurality of field effect transistors comprising: a first rectifier field effect transistor having its second and third terminals connected to said lower voltage point and its first terminal connected to a terminal to which a clock signal is applied through said capacitance means; a second rectifier field effect transistor having its second and third terminals connected to said first terminal of said first rectifier field effect transistor and its first terminal connected to a low-level voltage point; and a clamp field effect transistor having its first terminal connected to said lower voltage point and its second and third terminals connected to a low-level voltage point.

Claim 11

An output circuit as claimed in claim 6, wherein a channel length of said first transistor is shorter than a channel length of said second transistor.