Digital test probe having memory for logic levels at different test locations

Claim 2

A digital test probe for determining logic levels at different test locations of a digital circuit comprising: an electrically conductive probe needle for making electrical contact with a said test location; logic level detection means connected to said needle for providing a data signal having a logic level representative of that at a said test location contacted by said needle; memory means having N storage locations each for storing a binary level signal indicative of the logic level at an associated one of N said test locations; N stored data indicator means coupled to said memory means for providing indications of the logic levels at associated ones of said N test locations; N location indicator means respectively associated with said N stored data indicator means for use in associating the binary level of the stored data with a test location; and data entry means, for entering each said data signal for storage in a storage location of said memory means associated with one of said N test locations.

Claim 3

A digital test probe as set forth in claim 1 wherein said data entry means includes addressing means for sequentially addressing each of said N storage locations of said memory means in response to sequentially provided data store pulses for sequentially entering N data signals in respective ones of said N storage locations.

Claim 4

A digital test probe as set forth in claim 2 including manually operable means for supplying said data store pulses to said data entry means.

Claim 5

A digital test probe as set forth in claim 3 wherein said means for providing said data store pulses includes switch means adapted to be operated by an operator for providing a said data store pulse.

Claim 6

A digital test probe as set forth in claim 3 wherein said electrically conductive probe needle is mounted within a probe body housing and spring biased therein so that when said needle is depressed against the test circuit it retracts within the probe body and switch means within said probe body operably connected to said needle for providing a said data store pulse each time said needle is depressed into said probe body.

Claim 7

A digital test probe as set forth in claim 1 wherein each of said stored data indicator means is connected to an associated one of said memory storage locations for providing a visual indication in dependence upon the binary level signal stored therein.

Claim 8

A digital test probe as set forth in claim 1 including a remote housing separate from but electrically connected to said probe needle, said stored data indicators being mounted on said remote housing.

Claim 9

A digital test probe as set forth in claim 1 wherein said data entry means includes addressing means for individually addressing each said location of said memory means for entering data for storage therein representative of the binary level of said data signal.

Claim 10

A digital test probe as set forth in claim 8, wherein said addressing means includes a counter for counting N data store pulses and having N outputs for respectively addressing one of said N storage locations in dependence upon the count therein.

Claim 11

A digital test probe as set forth in claim 9 including N indicator means each connected to one of said N outputs of said counter for providing a visual indication dependent upon the count therein so as to thereby indicate the last memory location for which data was entered into said memory means.

Claim 12

A digital test probe as set forth in claim 9 including means for periodically supplying a data store pulse for application to said binary counter to increment the count therein.

Claim 13

A digital test probe as set forth in claim 11 wherein said data store pulse supplying means includes manually operable switch means for supplying a said data store pulse each time the operator desires to enter said data signal for storage in said memory means.

Claim 14

A digital test probe for use in determining logic levels at various test locations of digital circuit, comprising: an elongated probe housing suitably configured to be held by one hand of an operator; an electrically conductive probe needle extending from one end of said housing for making electrical contact with test locations of said digital circuit; binary level detection means connected to said needle for providing a data signal having a binary level representative of that at a said test location contacted by said needle; data storage means for storing N said data signals and including a multistage register having N addressable stages each for storing data representative of the binary level at an associated one of N said test locations; N data stored indicator means each coupled to an associated one of said register stages for providing a visual indication of the binary level of the data signal stored therein; N address location indicator means coupled to said counter means and responsive thereto such that one of said location indicator means will be energized to provide a visual display in accordance with the count in said counter means; and data entry means for entering each said data signal for storage in said register at a location of said addressable stages associated with one of said test locations.

Claim 15

A digital test probe for use in determining logic levels at various test locations of digital circuit, comprising: an elongated probe housing suitably configured to be held by one hand of an operator; an electrically conductive probe needle extending from one end of said housing for making electrical contact with test locations of said digital circuit; binary level detection means connected to said needle for providing a data signal having a binary level representative of that at a said test location contacted by said needle; data storage means for storing N said data signals and including a multistage register having N addressable stages each for storing data representative of the binary level at an associated one of N said test locations; N data stored indicator means each coupled to an associated one of said register stages for providing a visual indication of the binary level of the data signal stored therein; N address location indicator means coupled to said counter means and responsive thereto such that one of said location indicator means will be energized to provide a visual display in accordance with the count in said counter means; and data entry means for entering each said data signal for storage in said register at a location of said addressable stages associated with one of said test locations.

Claim 16

A digital test probe as set forth in claim 13 wherein said data entry means includes means for sequentially addressing said N stages of said register in sequence with the provision of N said data signals from testing at N said test locations.

Claim 17

A digital test probe as set forth in claim 14 wherein said data entry means includes manually operable switch means for providing a data store pulse each time it is desired to enter a data signal for storage.

Claim 18

A digital test probe as set forth in claim 15, wherein said addressing means includes counter means responsive to each said data store pulse for addressing one of said register stages in dependence upon the count therein for entering data in the addressed register stage.

Claim 19

A digital test probe as set forth in claim 13, wherein said N data stored indicator means are mounted on said probe housing so as to be visually observable from the exterior thereof.

Claim 20

A digital test probe as set forth in claim 17, wherein said N stored data indicator means and said N address location indicator means are mounted on said probe housing so as to be visually observable from the exterior thereof.

Claim 21

A digital test probe as set forth in claim 18 wherein said stored data indicator means and said address location indicator means are arranged such that each location indicator means is physically associated with one of said data indicator means.