US4575796A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Information processing unit
Assignee: NEC Electronics Corp
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Filing: 1985-02-13
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Granted: 1986-03-11
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Expires: 2005-02-13
Abstract
Abstract An information processing unit designed for operating on N-bit bytes is capable of handling 2N-bit bytes in parallel. Control multiplexers selectively switch the connections between read and write buffers and a pair of bus lines. When 2N-bit processing is needed the multiplexers alter the connection between the bus lines and the buffers. The altered connection plus other normal buffer to bus line connections permit an increase in the data length that can be read or written simultaneously.
Inventors
- 👤 Ikutaro Wako
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:30
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1647; G06F12/00; G06F12/02; G06F12/04; G06F13/1668; G06F13/1678
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
482 words
An information processing unit of the type adapted for handling N-bit data in parallel, said unit comprising, first and second N-bit bus lines, a random access memory (RAM) having first and second halves, a first read buffer circuit for coupling N-bit data read from said first half of said RAM to said first bus line, a first write buffer circuit for coupling N-bit data from said second bus line into said first half of said RAM, a first multiplexer and a second multiplexer, a second read buffer circuit for coupling N-bit data read from said second half of said RAM to said first multiplexer, said first multiplexer being coupled to said first and second bus lines and operative to selectively couple N-bit data from said second read buffer to said first and second bus lines, a second write buffer for coupling N-bit data from said second multiplexer to be written into said second half of said RAM, said second multiplexer being coupled to said first and second bus lines and operative to selectively couple N-bit data from said first and second bus lines to said second write buffer, and control means for generating first, second and third control signals, N-bit data stored in said first half of said RAM being transferred to said first bus line through said first read buffer in response to said first control signal, N-bit data stored in said second half of said RAM being transferred to said first bus line through said second read buffer and said first multiplexer in response to said second control signal, 2N-bit data stored in said first and second halves of said RAM being simultaneously transferred to said first and second bus lines, respectively, in response to said third control signal such that N-bit data stored in said first half of said RAM is transferred through said first read buffer to said first bus line and N-bit data stored in said second half of said RAM is transferred through said second read buffer and said first multiplexer to said second data bus, N-bit data on said first bus line being written into said first half of said RAM through said first write buffer in response to said first control signal, N-bit data on said first bus line being written into said second half of said RAM through said second multiplexer and said second write buffer in response to said second control signal, 2N-bit data on said first and second bus lines, respectively, being simultaneously written into said first and second halves of said RAM in response to said third control signals such that the N-bit data on said first bus line is transferred through said first write buffer to said first half of said RAM, and the N-bit data on said second bus line is transferred through said second multiplexer and said second write buffer to said second half of said RAM.
Claim 2
Dependent Claim
482 words
An information processing unit of the type adapted for handling N-bit data in parallel, said unit comprising, first and second N-bit bus lines, a random access memory (RAM) having first and second halves, a first read buffer circuit for coupling N-bit data read from said first half of said RAM to said first bus line, a first write buffer circuit for coupling N-bit data from said second bus line into said first half of said RAM, a first multiplexer and a second multiplexer, a second read buffer circuit for coupling N-bit data read from said second half of said RAM to said first multiplexer, said first multiplexer being coupled to said first and second bus lines and operative to selectively couple N-bit data from said second read buffer to said first and second bus lines, a second write buffer for coupling N-bit data from said second multiplexer to be written into said second half of said RAM, said second multiplexer being coupled to said first and second bus lines and operative to selectively couple N-bit data from said first and second bus lines to said second write buffer, and control means for generating first, second and third control signals, N-bit data stored in said first half of said RAM being transferred to said first bus line through said first read buffer in response to said first control signal, N-bit data stored in said second half of said RAM being transferred to said first bus line through said second read buffer and said first multiplexer in response to said second control signal, 2N-bit data stored in said first and second halves of said RAM being simultaneously transferred to said first and second bus lines, respectively, in response to said third control signal such that N-bit data stored in said first half of said RAM is transferred through said first read buffer to said first bus line and N-bit data stored in said second half of said RAM is transferred through said second read buffer and said first multiplexer to said second data bus, N-bit data on said first bus line being written into said first half of said RAM through said first write buffer in response to said first control signal, N-bit data on said first bus line being written into said second half of said RAM through said second multiplexer and said second write buffer in response to said second control signal, 2N-bit data on said first and second bus lines, respectively, being simultaneously written into said first and second halves of said RAM in response to said third control signals such that the N-bit data on said first bus line is transferred through said first write buffer to said first half of said RAM, and the N-bit data on said second bus line is transferred through said second multiplexer and said second write buffer to said second half of said RAM.
Claim 3
Dependent Claim
290 words
An information processing unit comprising a first data bus for transferring information, a second data bus for transferring information, first storing means for storing information, second storing means for storing information, a first connection bus coupling said first storing means to said first data bus, coupling means inserted between said first and second data buses and said second storing means, a second connection bus coupling said first data bus to said coupling means, a third connection bus coupling said second data bus to said coupling means, a fourth connection bus coupling said coupling means to said second storing means, accessing means coupled to said first storing means and said second storing means and generating first, second and third access signals, and control means coupled to said coupling means, said first storing means transferring information stored therein to said first data bus through said first connection bus in response to said first access signal and said third access signal, said control means controlling said coupling means such that information stored in said second storing means is transferred to said first data bus through said fourth connection bus and said second connection bus in response to said second access signal at a different time from a time when information stored in said first storing means is transferred to said first data bus in response to said first access signal, and information stored in said second storing means is transferred to said second data bus through said fourth connection bus and said third connection bus in response to said third access signal at the same time as information stored in said first storing means is transferred to said first data bus through said first connection bus in response to said third access signal.
Claim 4
Dependent Claim
290 words
An information processing unit comprising a first data bus for transferring information, a second data bus for transferring information, first storing means for storing information, second storing means for storing information, a first connection bus coupling said first storing means to said first data bus, coupling means inserted between said first and second data buses and said second storing means, a second connection bus coupling said first data bus to said coupling means, a third connection bus coupling said second data bus to said coupling means, a fourth connection bus coupling said coupling means to said second storing means, accessing means coupled to said first storing means and said second storing means and generating first, second and third access signals, and control means coupled to said coupling means, said first storing means transferring information stored therein to said first data bus through said first connection bus in response to said first access signal and said third access signal, said control means controlling said coupling means such that information stored in said second storing means is transferred to said first data bus through said fourth connection bus and said second connection bus in response to said second access signal at a different time from a time when information stored in said first storing means is transferred to said first data bus in response to said first access signal, and information stored in said second storing means is transferred to said second data bus through said fourth connection bus and said third connection bus in response to said third access signal at the same time as information stored in said first storing means is transferred to said first data bus through said first connection bus in response to said third access signal.
Claim 5
Dependent Claim
26 words
The unit as claimed in claim 2, in which said first storing means is directly coupled only to said first data bus via a buffer circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-10 | 1989-09-09 | 1990-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-10 | 1993-09-09 | 1994-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-10 | 1997-09-09 | 1998-03-11 | $7700.00 | Window Closed / Lapsed |