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US4581626A Expired / Lapsed US ⏱️ 0.0 years remaining

Thyristor cathode and transistor emitter structures with insulator islands

Assignee: Fairchild Semiconductor Corp
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Filing: 1979-04-09
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Granted: 1986-04-08
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Expires: 1999-04-09
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Abstract

Abstract A gate turn-off (IGTO) thyristor having short turn-off times and high di/dt and dV/dt capabilities comprises an insulating layer overlying the inner region of the n2-emitter (cathode) region which includes a central region of greater resistivity than the n2-emitter cathode region for reducing turn-off current density of the device. The addition of an insulating layer and a central region of increased resistivity to the central portions of a base region of a bipolar transistor provides similar improved performance characteristics.

Inventors

  • 👤 Surinder Krishna
  • 👤 E. Duane Wolley

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 22:14
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10D18/00; H10D18/60; H10D62/141; H10D62/148; H10D64/00; H10D64/20; H10D64/23; H10D64/231; H10D64/233

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 198 words
In a bipolar transistor semiconductor device having an emitter terminal and a collector terminal, and a base terminal for controlling current flow through said collector and emitter terminals, and wherein said device includes a semiconductor wafer having three regions of alternating conductivity type overlying each other, the inner region comprising the base region and the outer regions comprising the emitter and collector regions of said device, the emitter region including a plurality of individual cellular regions, the improvement comprising: a plurality of adjacently spaced regions of predetermined resistivity extending from said base region substantially centrally into each of said cellular regions, respectively, each of said regions of predetermined resistivity being of higher resistivity than its respective surrounding cellular region, each of said cellular regions extending into said base region from a common surface thereof so as to be completely surrounded by said base region; a base electrode situated atop said base region and surrounding each of said cellular regions; an insulating layer overlying each said region of predetermined resistivity, respectively, for precluding any significant current flow from said base to said cellular regions during the nonconducting state of said device; and conductive means electrically interconnecting said cellular regions.
Claim 2
Dependent Claim 198 words
In a bipolar transistor semiconductor device having an emitter terminal and a collector terminal, and a base terminal for controlling current flow through said collector and emitter terminals, and wherein said device includes a semiconductor wafer having three regions of alternating conductivity type overlying each other, the inner region comprising the base region and the outer regions comprising the emitter and collector regions of said device, the emitter region including a plurality of individual cellular regions, the improvement comprising: a plurality of adjacently spaced regions of predetermined resistivity extending from said base region substantially centrally into each of said cellular regions, respectively, each of said regions of predetermined resistivity being of higher resistivity than its respective surrounding cellular region, each of said cellular regions extending into said base region from a common surface thereof so as to be completely surrounded by said base region; a base electrode situated atop said base region and surrounding each of said cellular regions; an insulating layer overlying each said region of predetermined resistivity, respectively, for precluding any significant current flow from said base to said cellular regions during the nonconducting state of said device; and conductive means electrically interconnecting said cellular regions.

References Cited (Backward Citations)

US3430115A Cited
US3432920A Cited
US3619738A Cited
US3902188A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-04-07 1989-10-07 1990-04-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-04-07 1993-10-07 1994-04-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-04-07 1997-10-07 1998-04-08 $7700.00 Window Closed / Lapsed

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