Semiconductor integrated circuit for squaring a signal with suppression of the linear component

Claim 2

In an integrated circuit, a circuit arrangement for producing an output signal which is a prescribed nonlinear function of an incoming signal comprising a pair of identical dual-ended linear amplifiers, each of the amplifiers connected for receiving the incoming signal and each of the amplifiers connected for delivering its output to a different one of a pair of identical dual-to-single-ended linear converters, and a nonlinear/summing device for nonlinearly transforming and summing the single-ended outputs of the converters to produce the output signal, in which coupling means of one of the dual-ended amplifiers cross-couple a pair of output terminals of the one amplifier to a pair of input terminals of the corresponding converter.

Claim 3

An integrated circuit including means for squaring an incoming signal comprising: (a) first and second identical dual-ended amplifiers, each of the amplifiers for receiving as input the incoming signal and each for developing a respective dual-ended output at a separate pair of amplifier output terminals thereof; (b) first and second identical dual-to-single-ended converters each having a separate single-ended output terminal, the first converter having a first pair of input terminals thereof coupled to the pair of output terminals of the first dual-ended amplifier, the second converter having a second pair of input terminals thereof of cross-coupled to the pair of output terminals of the second dual-ended amplifier; and (c) a summer/squarer network connected for receiving, squaring, and summing the signals from the single-ended output terminals of the first and second converters.

Claim 4

An integrated circuit including means for squaring an incoming signal comprising: (a) first and second identical dual-ended amplifiers, each of the amplifiers for receiving as input the incoming signal and each for developing a respective dual-ended output at a separate pair of amplifier output terminals thereof; (b) first and second identical dual-to-single-ended converters each having a separate single-ended output terminal, the first converter having a first pair of input terminals thereof coupled to the pair of output terminals of the first dual-ended amplifier, the second converter having a second pair of input terminals thereof of cross-coupled to the pair of output terminals of the second dual-ended amplifier; and (c) a summer/squarer network connected for receiving, squaring, and summing the signals from the single-ended output terminals of the first and second converters.

Claim 5

The circuit of claim 2 in which each amplifier is a difference amplifier comprising a separate pair of MOS inverters connected mutually in parallel, each such amplifier connected for being supplied by a source of the same constant current, one of the inverters in each of such amplifiers for receiving as input the incoming signal and the other of the inverters in each of such amplifiers for receiving as input a reference voltage.

Claim 6

The circuit of claim 3 in which each of the inverters has an input MOS transistor connected in series with a load.

Claim 7

The circuit of claim 4 in which each load is an MOS transistor having the same transconductance as the input MOS transistor.

Claim 8

The circuit of claim 3 in which the reference voltage is ground potential.

Claim 9

The circuit of claim 5 in which each converter comprises a separate pair of input MOS transistors and a separate pair of output MOS transistors, each such input transistor of each converter being connected in series with a different one of the output transistors of the converter, both output transistors of each converter having gate terminals which are connected together and to one of the input transistors of the converter.

Claim 10

The circuit of claim 4 in which each converter comprises a separate pair of input MOS transistors and a separate pair of output MOS transistors, each such input transistor of each converter being connected in series with a different one of the output transistors of the converter, both output transistors of each converter having gate terminals which are connected together and to one of the input transistors of the converter.

Claim 11

The circuit of claim 3 in which each converter comprises a separate pair of input MOS transistors and a separate pair of output MOS transistors, each such input transistor of each converter being connected in series into a different one of the output transistors of the converter, both output transistors of each converter having gate terminals which are connected together and to one of the input transistors of the converter.

Claim 12

An integrated squarer circuit comprising: (a) first and second dual-ended amplifiers each having a pair of identical parallel branches connected together in series with a separate identical bias current source, each of the branches having a separate input MOS transistor connected in series with a separate load MOS transistor, the input transistor in one branch of each of the first and second amplifiers being connected for receiving a signal to be squared by the circuit, the input transistor in the other branch of each of the first and second amplifiers being connected for receiving a reference voltage, the first and second amplifiers having a separate negative output node located between the input and output transistors of the one branch of the respective amplifier and having a separate positive output node located between the input and output transistors of the other branch of the respective amplifiers; (b) first and second dual-to-single-ended converters, each having a separate pair of parallel branches, each branch having a separate input MOS transistor connected in series with a separate output MOS transistor, the input transistors of one branch of each of the first and second converters, respectively, having a gate terminal connected to the negative output node of the first and second amplifiers, respectively, the input transistors of the other branches of the first and second converters, respectively, having a gate terminal connected to the positive output node of the first and second amplifiers, respectively, the output transistors of the one branch of the first converter having a gate terminal connected to its source terminal and to a gate terminal of the output transistor of the other branch of the first converter, and the output transistors of the other branch of the second converter having a gate terminal connected to its source terminal and to a gate terminal of the one branch of the second converter, the first converter having an output node located between the input and output transistors of the other branch thereof, the second converter having an output node located between the input and output transistors of the one branch thereof; and (c) a summer/squarer network connected for receiving, squaring, and summing the signals developed at the output node of the first and second converters.

Claim 13

An integrated squarer circuit comprising: (a) first and second dual-ended amplifiers each having a pair of identical parallel branches connected together in series with a separate identical bias current source, each of the branches having a separate input MOS transistor connected in series with a separate load MOS transistor, the input transistor in one branch of each of the first and second amplifiers being connected for receiving a signal to be squared by the circuit, the input transistor in the other branch of each of the first and second amplifiers being connected for receiving a reference voltage, the first and second amplifiers having a separate negative output node located between the input and output transistors of the one branch of the respective amplifier and having a separate positive output node located between the input and output transistors of the other branch of the respective amplifiers; (b) first and second dual-to-single-ended converters, each having a separate pair of parallel branches, each branch having a separate input MOS transistor connected in series with a separate output MOS transistor, the input transistors of one branch of each of the first and second converters, respectively, having a gate terminal connected to the negative output node of the first and second amplifiers, respectively, the input transistors of the other branches of the first and second converters, respectively, having a gate terminal connected to the positive output node of the first and second amplifiers, respectively, the output transistors of the one branch of the first converter having a gate terminal connected to its source terminal and to a gate terminal of the output transistor of the other branch of the first converter, and the output transistors of the other branch of the second converter having a gate terminal connected to its source terminal and to a gate terminal of the one branch of the second converter, the first converter having an output node located between the input and output transistors of the other branch thereof, the second converter having an output node located between the input and output transistors of the one branch thereof; and (c) a summer/squarer network connected for receiving, squaring, and summing the signals developed at the output node of the first and second converters.

Claim 14

The circuit of claim 10 in which the summer/squarer network comprises a pair of input MOS transistors mutually connected in parallel and connected together in series with a load for biasing the input transistors of the network in a nonlinear region, one of the input transistors thereof having a gate terminal connected to the output node of the first converter and the other of the input transistors thereof having a gate terminal connected to the output node of the second converter, whereby during operation the square of the signal is developed at a node located between the input transistors and the load of the converter.

Claim 15

The circuit of claim 11 in which the summer/squarer network consists of a pair of input MOS transistors mutually connected in parallel and connected together in series with a load for biasing the input transistors of the network in a nonlinear region, one of the input transistors thereof having a gate terminal connected to the output node of the first converter and the other of the input transistors thereof having a gate terminal connected to the output node of the second converter, whereby during operation the square of the signal is developed at a node located between the input transistors and the load of the converter.

Claim 16

The circuit of claim 10 in which the transconductances of the input transistor of the amplifier are equal to the transconductances of the output transistors of the amplifiers.