US4590601A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pseudo random framing detector circuit
Assignee: AG Communication Systems Corp
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Filing: 1984-12-24
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Granted: 1986-05-20
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Expires: 2004-12-24
Abstract
Abstract This invention is a circuit for detecting a framing pattern consisting of a pseudo random shift register sequence. This circuit utilizes an extremely long framing pattern without either a large amount of memory or the need to receive a large number of bits in order to recognize the framing pattern. The use of lengthy framing patterns minimizes the chance of false framing caused by patterns in bit positions other than the framing bit position. In addition, the incoming data stream may be connected directly to the shift register mechanism.
Inventors
- 👤 Robert H. Beeman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:02
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0611
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
392 words
In a digital telecommunications system, a pseudo random framing detector circuit for recovering periodic framing data and transmitting said framing data to logic of said system, said framing data being interleaved with transmission data received from another digital telecommunications system via transmission equipment, said pseudo random framing detector circuit comprising: clock means connected to said transmission equipment and being operated to produce a periodic clock signal of a predetermined frequency in response to said interleaved data; frame sizing means connected to said clock means and being operated in response to said periodic clock signal to produce a second periodic signal of a period equal to the length in bits of said framing data and said transmission data; gating means; shift-register means connected to said frame sizing means and, via a switching means, to said transmission equipment, said shift-register means including a plurality of tap outputs and an input, said shift-register means being cyclically operated in response to said second periodic signal to produce a plurality of tap output signals on said corresponding plurality of tap outputs, at least two of said tap outputs being connected to said gating means and each said connected tap output being a logic one bit positional representation corresponding to any polynomial of maximal length for a particular size of said shift-register means; said gating means connected to said logic one bit positions of said tap outputs, said gating means being cyclically operated in response to said connected tap output signals to produce said framing data; framing control means; said switching means connected to said transmission equipment, to said framing control means, to said gating means and to said input of said shift-register means, said switching means being operated in response to said framing control means to connect said gating means to said input of said shift-register means or said switching means being operated in response to said framing control means to connect said transmission equipment to said input of said shift-register means; said framing control means further connected to said frame sizing means, said framing control means being operated to select said switching means to input said framing data to said shift-register means or to input said interleaved data to said shift-register means; and said framing control means connected to said logic and being further operated to transmit said framing data to said logic of said system.
Claim 2
Dependent Claim
392 words
In a digital telecommunications system, a pseudo random framing detector circuit for recovering periodic framing data and transmitting said framing data to logic of said system, said framing data being interleaved with transmission data received from another digital telecommunications system via transmission equipment, said pseudo random framing detector circuit comprising: clock means connected to said transmission equipment and being operated to produce a periodic clock signal of a predetermined frequency in response to said interleaved data; frame sizing means connected to said clock means and being operated in response to said periodic clock signal to produce a second periodic signal of a period equal to the length in bits of said framing data and said transmission data; gating means; shift-register means connected to said frame sizing means and, via a switching means, to said transmission equipment, said shift-register means including a plurality of tap outputs and an input, said shift-register means being cyclically operated in response to said second periodic signal to produce a plurality of tap output signals on said corresponding plurality of tap outputs, at least two of said tap outputs being connected to said gating means and each said connected tap output being a logic one bit positional representation corresponding to any polynomial of maximal length for a particular size of said shift-register means; said gating means connected to said logic one bit positions of said tap outputs, said gating means being cyclically operated in response to said connected tap output signals to produce said framing data; framing control means; said switching means connected to said transmission equipment, to said framing control means, to said gating means and to said input of said shift-register means, said switching means being operated in response to said framing control means to connect said gating means to said input of said shift-register means or said switching means being operated in response to said framing control means to connect said transmission equipment to said input of said shift-register means; said framing control means further connected to said frame sizing means, said framing control means being operated to select said switching means to input said framing data to said shift-register means or to input said interleaved data to said shift-register means; and said framing control means connected to said logic and being further operated to transmit said framing data to said logic of said system.
Claim 3
Dependent Claim
66 words
A pseudo random framing detector circuit as claimed in claim 1, said shift-register means including a clock input connected to said frame sizing means via a second periodic signal lead corresponding to said second periodic signal, said shift-register means being operated to displace by one bit position each current tap output signal unidirectionally and to produce said displaced tap output signals on said connected tap outputs.
Claim 4
Dependent Claim
19 words
A pseudo random framing detector circuit as claimed in claim 2, said gating means including exclusive OR gating means.
Claim 5
Dependent Claim
56 words
A pseudo random framing detector circuit as claimed in claim 3, said exclusive OR gating means including a plurality of inputs and at least one output, said logic one tap outputs being connected to corresponding ones of said exclusive OR gating means inputs and said exclusive OR gating means output being connected to said switching means.
Claim 6
Dependent Claim
32 words
A pseudo random framing detector circuit as claimed in claim 4, said framing control means being further connected to said output of said exclusive OR gating means for receiving said framing data.
Claim 7
Dependent Claim
42 words
A pseudo random framing detector circuit as claimed in claim 5, said framing control means being further connected to said frame sizing means, said frame sizing means being operated in response to said framing control means to restart said second periodic signal.
Claim 8
Dependent Claim
57 words
A pseudo random framing detector circuit as claimed in claim 6, said framing control means being further connected to said transmission equipment and said framing control means being further operated in response to said framing data of said gating means and in response to said interleaved data of said transmission equipment to selectively operate said switching means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-19 | 1989-11-18 | 1990-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-19 | 1993-11-18 | 1994-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-19 | 1997-11-18 | 1998-05-20 | $7700.00 | Window Closed / Lapsed |