Failure detection apparatus for use with digital pads

Claim 1

In a digital switching system including a digital switching network for transmitting PCM data samples through said switching network between subscriber interface equipments via digital pads, failure detection apparatus for use with said digital pads comprising: said digital switching network connected between said subscriber interface equipments via said digital pads said digital switching network being operated to transmit pluralities of said PCM samples between subscribers connected to said subscriber interface equipments; each of said PCM data samples including a first plurality of data bits representing a magnitude value of said data samples, a second plurality of data bits and a first data parity bit representing parity over said first and second pluralities of data bits; means for storing connected between said network and said subscriber interface equipment, said means for storing being operated in response to said first plurality of bits of each said PCM data sample to produce a corresponding modulated magnitude value of each said PCM data sample for transmission to said subscriber interface equipment; said means for storing including parity generator means connected to said network and to said subscriber interface equipment, said parity generator means being operated to transmit a selected one of a stored plurality of second data parity bits representing the difference of parity between said magnitude value of each said PCM sample and said corresponding modulated magnitude value; gating means connected to said network and to said parity generator means, said gating means being operated in response to said first and second data parity bits to produce a third data parity bit over said PCM data sample including said modulated magnitude value and said second plurality of bits; parity checking means connected to said network, to said subscriber interface equipment, to said means for storing, and to said gating means, said parity checking being operated to calculate correct data parity over each said PCM data sample including said modulated magnitude value and said second plurality of bits, said parity checking means being further operated to compare said calculated correct data parity with said third data parity bit and to produce a first signal for a miscomparison of said bits indicating a failure of said digital pads; processor means connected to said digital switching network, to said parity generator means and to said parity checking means, said processor means being operated to receive said first signal indicating said miscomparison and to reconfigure said digital switching network in response to a predetermined number of said miscomparisons; said means for storing further including programmable read only memory means connected to said network, said programmable read only memory means containing a plurality of modulated magnitude values corresponding to each said PCM data sample transmitted by said digital switching network; said processor means further including a plurality of connections to said programmable read only memory means; and said programmable read only memory means being operated in response to said processor means to select one of said plurality of modulated magnitude values for each said corresponding PCM data sample.