Frequency synthesizer having jitter compensation

Claim 2

A frequency synthesizer comprising a reference frequency generator coupled to a frequency control circuit which includes a variable frequency reduction means including a cycle cancellation icrcuit arranged to cancel a cycle of the frequency to be reduced by the variable frequency reduction means for each input pulse to the cycle cancellation circuit from an offset frequency generator, the offset frequency generator being arranged to produce n pulses for each group of x pulses of a given frequency Fr to provide a variable offset frequency (n/x)Fr where n is an integer smaller than x, and further comprising a jitter compensation signal circuit connected to the frequency control circuit, an output of the jitter compensation signal circuit being arranged such that a compensation signal at the output causes compensation, at least partly, for any jitter in the period of the output frequency of the synthesizer that would otherwise be caused as a result of each cancelled cycle, the jitter compensation signal circuit deriving the compensation signal as a function of the offset frequency via an analogue integrator, characterized in that the jitter compensation signal circuit further includes means for generating, with respect to a given d.c. level, a bidirectional signal such that, for each group of x periods of the given frequency Fr, there are n periods over each of which an integral of the bidirectional signal is proportional to -(x-n), and (x-n) periods of the given frequency Fr over each of which an integral of the bidirectional signal is correspondingly proportional to n.

Claim 3

A frequency synthesizer as claimed in claim 1, wherein the bidirectional signal consists of a train of bidirectional pulses with respect to the given d.c. level such that one pulse occurs during every Fr period.

Claim 4

A frequency synthesizer as claimed in claim 2, wherein the pulses in the bidirectional pulse train have a constant amplitude and the integral over each Fr period is controlled by varying the pulse widths.

Claim 5

A frequency synthesizer as claimed in claim 1, 2, or 3 wherein the integral of the bidirectional signal over any Fr period is an inverse function of the output frequency.

Claim 6

A frequency synthesizer as claimed in claim 1, 2 or 3, wherein the variable frequency reduction means further includes means for, independently of any cycles cancelled by said input pulses from the offset frequency generator, adding cycles to and subtracting cycles from the frequency to be reduced such that an average number of added cycles is substantially equal to an average number of subtracted cycles, and further comprising means for, in each period of the given frequency Fr in which a cycle is added or subtracted, increasing the integral of the bidirectional signal over that Fr period by an amount proportional to x.

Claim 7

A frequency synthesizer comprising a reference frequency generator and a circuit for producing an output signal the frequency of which has a specific but variable ratio to that of an output signal of said reference frequency generator, said circuit having a first input for a reference frequency, the first input being coupled to the output of said reference frequency generator, a second input for a control signal for the phase of an output signal of said circuit, and an output coupled to an output of the synthesizer, said circuit including a frequency divider arrangement having a variable division ratio which determines said specific but variable ratio, said frequency divider arrangement including means for periodically cancelling an effect which a cycle of an input signal to said arrangement would otherwise have on an output signal of said arrangement and thereby each time delaying an occurrence of a next cyle of the output signal of said arrangement, the delay of the next cycle occurring for n out of every x cycles of the output of signal of said arrangement, the synthesizer further comprising a coupling to the second input from a point in said circuit at which occurs a signal containing information about jitter which would otherwise occur in the period of the output signal of said circuit due to jitter in the period of the output signal of said frequency divider arrangement caused by operation of said means, for applying a control signal to said second input to thereby compensate for the jitter which would otherwise occur in the output signal of said circuit, said coupling including an analog integrator, characterized in that said coupling also includes, prior to said analog integrator, means for generating, with respect to a given d.c. level, a bidirectional signal an integral of which is proportional to -(x-n) over each period occupied by a cycle of the output signal of said arrangement which immediately precedes a delayed cycle of the output signal of said arrangement and is proportional to n over each period occupied by a cycle of the output signal of said arrangement which does not immediately precede a delayed cycle of the output signal of said arrangement.

Claim 8

A frequency synthesizer comprising a reference frequency generator and a circuit for producing an output signal the frequency of which has a specific but variable ratio to that of an output signal of said reference frequency generator, said circuit having a first input for a reference frequency, the first input being coupled to the output of said reference frequency generator, a second input for a control signal for the phase of an output signal of said circuit, and an output coupled to an output of the synthesizer, said circuit including a frequency divider arrangement having a variable division ratio which determines said specific but variable ratio, said frequency divider arrangement including means for periodically cancelling an effect which a cycle of an input signal to said arrangement would otherwise have on an output signal of said arrangement and thereby each time delaying an occurrence of a next cyle of the output signal of said arrangement, the delay of the next cycle occurring for n out of every x cycles of the output of signal of said arrangement, the synthesizer further comprising a coupling to the second input from a point in said circuit at which occurs a signal containing information about jitter which would otherwise occur in the period of the output signal of said circuit due to jitter in the period of the output signal of said frequency divider arrangement caused by operation of said means, for applying a control signal to said second input to thereby compensate for the jitter which would otherwise occur in the output signal of said circuit, said coupling including an analog integrator, characterized in that said coupling also includes, prior to said analog integrator, means for generating, with respect to a given d.c. level, a bidirectional signal an integral of which is proportional to -(x-n) over each period occupied by a cycle of the output signal of said arrangement which immediately precedes a delayed cycle of the output signal of said arrangement and is proportional to n over each period occupied by a cycle of the output signal of said arrangement which does not immediately precede a delayed cycle of the output signal of said arrangement.

Claim 9

A synthesizer as claimed in claim 6, wherein the bidirectional signal consists of a train of bidirectional pulses with respect to said given d.c. level such that one pulse occurs in each period occupied by a cycle of the output signal of said arrangement.

Claim 10

A synthesizer as claimed in claim 7, wherein pulses of the bidirectional signal have a constant amplitude and an integral over each period occupied by a cycle of the output signal of said arrangement is controlled by varying the pulse widths.

Claim 11

A synthesizer as claimed in claim 6, 7, or 8, wherein the integral of the bidirectional signal over each period occupied by a cycle of the output signal of said arrangement is an inverse function of the frequency of the output signal of said circuit.

Claim 12

A modification of a synthesizer as claimed in claim 6, 7, or 8, wherein said frequency divider arrangement further includes means for periodically cancelling an effect which a further cycle of the input signal to said arrangement would otherwise have on the output signal of said arrangement and periodically creating in the output signal of said arrangement an effect of substantially a same number of cycles as said further cycles added to the input signal of said arrangement so that overall, for each cycle of the output signal of said arrangement, an occurrence of a next cycle of said output signal will either (a) be delayed by one period of the input signal of said arrangement, (b) be delayed by two periods of the input signal of said arrangement, (c) be advanced by one period of the input signal of said arrangement, or (d) be neither advanced nor delayed, said means for generating a bidirectional signal being constructed to generate a bidirectional signal an integral of which over each period occupied by a cycle of the output signal of said arrangement is proportional to -(x-n) in case (a), -(2x-n) in case (b), (n+x) in case (c), and n in case d.

Claim 13

A modification of a synthesizer as claimed in claim 9, wherein said frequency divider arrangement further includes means for periodically cancelling an effect which a further cycle of the input signal to said arrangement would otherwise have on the output signal of said arrangement and periodically creating in the output signal of said arrangement an effect of substantially a same number of cycles as said further cyles added to the input signal of said arrangement so that overall, for each cycle of the output signal of said arrangement, an occurrence of a next cycle of said output signal will either (a) be delayed by one period of the input signal of said arrangement, (b) be delayed by two periods of the input signal of said arrangement, (c) be advanced by one period of the input signal of said arrangement, or (d) be neither advanced nor delayed, said means for generating a bidirectional signal being constructed to generate a bidirectional signal an integral of which over each period occupied by a cycle of the output signal of said arrangment is proportional to -(x-n) in case (a), -(2x-n) in case (b), (n+x) in case (c), and n in case d.

Claim 14

A frequency synthesizer comprising a reference frequency generator and a circuit for producing an output signal the frequency of which has a specific but variable ratio to that of an output signal of said reference frequency generator, said circuit having a first input for a reference frequency, the first input being coupled to the output of said reference frequency generator, a second input for a control signal for the phase of the output signal of said circuit, and an output coupled to an output of the synthesizer, said circuit including a frequency divider arrangement having a variable division ratio which determines said specific but variable ratio, said frequency divider arrangement including means for periodically cancelling an effect which a cycle of an input signal to said arrangement would otherwise have on the output signal of said arrangment and thereby each time supressing a cycle of the output signal of said arrangement which would otherwise occur, the suppression of a cycle of the output signal of said arrangement occurring for n out of every x cycles of the output signal of said arrangement which would otherwise occur, the synthesizer further comprising a coupling to the second input from a point in said circuit at which occurs a signal containing information about jitter which would otherwise occur in the period of the output signal of said circuit due to jitter in the period of the output signal of said frequency divider arrangement caused by operation of said means, for applying a control signal to said second input to thereby compensate for the jitter which would otherwise occur in the output signal of said circuit, said coupling including an analog integrator, characterized in that said coupling also includes, prior to said analog integrator, means for generating, with respect to a given d.c. level, a bidirectional signal an integral of which is proportional to -(x-n) over each period during which a cycle of the output signal of said arrangement which would otherwise occur is suppressed and is proportional to n over each period during which a cycle of the output signal of said arrangement is not suppressed.

Claim 15

A frequency synthesizer comprising a reference frequency generator and a circuit for producing an output signal the frequency of which has a specific but variable ratio to that of an output signal of said reference frequency generator, said circuit having a first input for a reference frequency, the first input being coupled to the output of said reference frequency generator, a second input for a control signal for the phase of the output signal of said circuit, and an output coupled to an output of the synthesizer, said circuit including a frequency divider arrangement having a variable division ratio which determines said specific but variable ratio, said frequency divider arrangement including means for periodically cancelling an effect which a cycle of an input signal to said arrangement would otherwise have on the output signal of said arrangment and thereby each time supressing a cycle of the output signal of said arrangement which would otherwise occur, the suppression of a cycle of the output signal of said arrangement occurring for n out of every x cycles of the output signal of said arrangement which would otherwise occur, the synthesizer further comprising a coupling to the second input from a point in said circuit at which occurs a signal containing information about jitter which would otherwise occur in the period of the output signal of said circuit due to jitter in the period of the output signal of said frequency divider arrangement caused by operation of said means, for applying a control signal to said second input to thereby compensate for the jitter which would otherwise occur in the output signal of said circuit, said coupling including an analog integrator, characterized in that said coupling also includes, prior to said analog integrator, means for generating, with respect to a given d.c. level, a bidirectional signal an integral of which is proportional to -(x-n) over each period during which a cycle of the output signal of said arrangement which would otherwise occur is suppressed and is proportional to n over each period during which a cycle of the output signal of said arrangement is not suppressed.

Claim 16

A synthesizer as claimed in claim 12, wherein the bidirectional signal consists of a train of bidirectional pulses with respect to said given d.c. level such that one pulse occurs in each said period during which a cycle of the output signal of said arrangement which would otherwise occur is suppressed and in each said period during which a cycle of the output signal of said arrangement is not suppressed.

Claim 17

A synthesizer as claimed in claim 13, wherein the pulses of the bidirectional signal have a constant amplitude and the integral over each said period during which a cycle of the output signal of said arrangement which would otherwise occur is suppressed and over each said period during which a cycle of the output signal of said arrangement is not suppressed is controlled by varying the pulse widths.