US4603341A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stacked double dense read only memory
Assignee: International Business Machines Corp
•
Filing: 1983-09-08
•
Granted: 1986-07-29
•
Expires: 2003-09-08
Abstract
Abstract A read only memory array of stacked IGFET devices composed of first and second sub-arrays of field effect transistors. The first sub-array of first field effect transistors is formed in a substrate. Each of the first field effect transistor devices is responsive to a polysilicon gate electrode. The second sub-array of second field effect transistors is formed in a layer of laser annealed polysilicon material which overlies the first sub-array. The gate electrodes of the first field effect transistors act as the gate electrodes of the second field effect transistors.
Inventors
- 👤 Claude L. Bertin
- 👤 Howard L. Kalter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:16
CPC Classifications
H; H10; H10B; H10B20/00; H10B41/00; H10B41/10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
124 words
An array of field effect devices including a first sub-array of interconnected first field effect devices having source and drain regions formed in a semiconductor substrate, each of the first field effect devices being responsive to a gate electrode, and a second sub-array including a plurality of interconnected second field effect devices having source and drain regions formed in a layer of semiconductor material overlying the first sub-array, the gate electrodes of the first field effect devices acting as the gate electrodes of the second field effect devices, wherein selected ones of said first and second field effect devices are enhancement mode devices of low threshold, the remaining ones of said first and second field effect devices being enhancement mode devices of high threshold.
Claim 2
Dependent Claim
124 words
An array of field effect devices including a first sub-array of interconnected first field effect devices having source and drain regions formed in a semiconductor substrate, each of the first field effect devices being responsive to a gate electrode, and a second sub-array including a plurality of interconnected second field effect devices having source and drain regions formed in a layer of semiconductor material overlying the first sub-array, the gate electrodes of the first field effect devices acting as the gate electrodes of the second field effect devices, wherein selected ones of said first and second field effect devices are enhancement mode devices of low threshold, the remaining ones of said first and second field effect devices being enhancement mode devices of high threshold.
Claim 3
Dependent Claim
27 words
In the array of field effect devices as claimed in claim 9, wherein said layer of semiconductor material overlying the first sub-array is laser annealed polycrystalline silicon.
Claim 4
Dependent Claim
107 words
An array of field effect devices including a first sub-array of interconnected first field effect devices having source and drain regions formed in a semiconductor substrate, each of the first field effect devices being responsive to a gate electrode of polycrystalline silicon, a second sub-array including a plurality of interconnected second field effect devices having source and drain regions formed in a layer of semiconductor material overlying the first sub-array, the gate electrodes of the first field effect devices acting as the gate electrodes of the second field effect devices, at least one word line of polycrystalline silicon integrally formed with a plurality of said gate electrodes.
Claim 5
Dependent Claim
107 words
An array of field effect devices including a first sub-array of interconnected first field effect devices having source and drain regions formed in a semiconductor substrate, each of the first field effect devices being responsive to a gate electrode of polycrystalline silicon, a second sub-array including a plurality of interconnected second field effect devices having source and drain regions formed in a layer of semiconductor material overlying the first sub-array, the gate electrodes of the first field effect devices acting as the gate electrodes of the second field effect devices, at least one word line of polycrystalline silicon integrally formed with a plurality of said gate electrodes.
Claim 6
Dependent Claim
27 words
In the array of field effect devices as claimed in claim 11, wherein said layer of semiconductor material overlying the first sub-array is laser annealed polycrystalline silicon.
Claim 7
Dependent Claim
48 words
In the array of field effect devices as claimed in claim 3, further including at least one select line connected to source regions of a plurality of said first and second field effect devices, said select line being silicided polycrystalline silicon within the said layer of semiconductor material.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-28 | 1990-01-27 | 1990-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-28 | 1994-01-27 | 1994-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-28 | 1998-01-27 | 1998-07-29 | $7700.00 | Window Closed / Lapsed |