Fast envelope detector with bias compensation

Claim 2

In combination with a host radar system receiving echo return signals, an envelope detection system with bias compensation comprising: an envelope detector receiving said echo return signals from said host radar system in the form of inphase and quadrature signal components and producing: a first output signal being a biased envelope detection signal; a second output signal being a mode select signal; a third output signal indicating a minimum value of the inphase and quadrature signal component; a fourth output signal indicating a maximum value of said inphase and quadrature signal component; a fifth output signal equaling the sum of said fourth output signal plus one-half said third output signal; and a bias compensation means receiving said first, second, third, fourth and fifth output signals from said envelope detector and producing an unbiased detection signal.

Claim 3

An envelope detection system as defined in claim 1 wherein said bias compensation means comprises: a programmable read-only memory receiving said second, third, fourth and fifth output signals from said envelope detector and using a first logic algorithm to produce a bias compensation signal when said second output signal indicates a normal bias compensation is required, said programmable read-only memory using a second logic algorithm to produce said bias compensation signal when said second output signal indicates a multiple divide-by-two envelope detection compensation is required; and an adding means receiving said biased envelope detection signal from said envelope detector and said bias compensation signal from said programmable read-only memory and producing said unbiased detection signal.

Claim 4

An envelope detecton system as defined in claim 2 wherein said first logic algorithm comprising the steps of: comparing said third output signal with said fourth output signal from said envelope detector; producing a bias compensation signal of logical 1 when said fourth output signal is a logical 1 and said output signal is zero; and producing a bias compensation signal of logical 0 otherwise.

Claim 5

An envelope detection system as defined in claim 3 wherein said second logic algorithm comprises the steps of: comparing said third, fourth and fifth output signals from said envelope detector; and producing a bias compensation signal using the following logic table: ______________________________________ PROM Min [I,Q] LSB Max [I,Q] LSB Sum LSB OUTPUT ______________________________________ 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 ______________________________________

Claim 6

An envelope detection system as defined in claim 4 wherein said adding means comprises: a binary adder combining said biased envelope detection signal with said bias compensation signal to produce said unbiased detection signal.